Emitter coupled flip flop memory with complementary bipolar load

Details Emitter coupled flip flop memory with complementary bipolar load Emitter coupled flip flop memory with complementary bipolar load

1981-01-26

1984-10-30

Larkins, William D.

Static information storage and retrieval

Systems using particular element

Flip-flop

357 14, 357 44, 357 46, 357 50, 357 51, 357 36, 365156, 307455, 307463, H01L 2704, G11C 1140

Patent

active

044803192

ABSTRACT:
Disclosed is a memory cell circuit including a pair of memory transistors having respective collectors and bases cross-coupled to each other, wherein load means connected to the collector of each one of said memory transistors comprises a parallel circuit of a load resistance and a transistor whose emitter and collector are connected to both ends of the load resistance and whose base is connected to the collector of the other of the memory transistors, thereby causing the readout currents of the memory cell circuit to be greater irrespective of increased load resistances.

REFERENCES:
patent: 3603820 (1971-09-01), Schnenemann
patent: 3693057 (1972-09-01), Wiedmann
patent: 4053923 (1977-10-01), Kang
patent: 4323913 (1982-04-01), Murrmann et al.
Ernst et al., Siemens Forsch, -u. Entwickl, -Ber., vol. 6, No. 2, 1977 (Springer-Verlag, NY, 1977), pp. 86-91.

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