Emitter area trim scheme for a PTAT current source

Details Emitter area trim scheme for a PTAT current source Emitter area trim scheme for a PTAT current source

2007-06-21

2008-10-28

Zweizig, Jeffrey S (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

External effect

Temperature

Reexamination Certificate

active

07443226

ABSTRACT:
A current source for generating a PTAT current using two bipolar transistors with an 1:A emitter area ratio implements a split resistor architecture to cancel mismatch errors in the current mirror of the current source. In one embodiment, a first resistor is coupled to the unit area bipolar transistor and a second resistor is coupled to the A-ratio-area bipolar transistor. The first resistor has a resistance value indicative of the emitter resistance reof the bipolar transistors while the second resistor has a resistance value satisfying the equation re*(lnA−1). In another embodiment, an emitter area trim scheme is applied in a PTAT current source to cancel, in one trim operation, both bipolar transistor area mismatch error and sheet resistance variations. The emitter area trim scheme operates to modify the emitter area of the A-ratio-area bipolar transistor to select the best effective emitter area that provides the most accurate PTAT current.

REFERENCES:
patent: 4350904 (1982-09-01), Cordell
patent: 5543746 (1996-08-01), Kuo
patent: 5604467 (1997-02-01), Matthews
patent: 6737908 (2004-05-01), Mottola et al.
patent: 6844772 (2005-01-01), Hoon et al.
patent: 7071767 (2006-07-01), Ou-yang et al.
patent: 7215183 (2007-05-01), Nakada

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