Top/bottom symmetrical protection scheme for flash

Details Top/bottom symmetrical protection scheme for flash Top/bottom symmetrical protection scheme for flash

2006-10-02

2008-08-05

Myers, Paul R (Department: 2111)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S163000

Reexamination Certificate

active

07409493

ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.

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