Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1999-08-31
2002-03-19
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S520000, C257S750000, C438S672000
Reexamination Certificate
active
06359329
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an embedded wiring having a single damascenel structure and a method for forming the same, more in detail to the embedded wiring structure having high reliability in electrical connection and the method for forming the same.
(b) Description of the Related Art
With the demand of miniaturization and high integration of semiconductor devices, wirings of the semiconductor device are made finer and multi-layered.
Because of this reason, in place of forming the wiring on a dielectric film, a so-called damascenel process is practiced which forms an embedded metal wiring in a trench of a dielectric film.
A conventional method of forming an embedded metal wiring having a single damascenel structure will be described referring to
FIGS. 1A
to
1
E showing sections of a wafer having the single Damasin structure in consecutive steps of fabrication.
As shown in
FIG. 1A
, a dielectric layer
11
, a wiring layer
12
, a first interlayer dielectric film
13
and an etch-stop layer
14
are sequentially formed on a substrate
10
.
Then, a via hole
18
which penetrates the etch-stop layer
14
and the first interlayer dielectric film
13
to reach the wiring layer
12
is formed as shown in FIG.
1
B.
The via hole
18
is filled with tungsten (W) formed as a conductive film by sputtering, and the W film on the etch-stop layer
14
is removed by etch-back to leave a via plug
20
as shown in FIG.
1
C.
Then, a second interlayer dielectric film
22
is formed on the etch-stop layer
14
, and a photoresist film (not shown) is formed on the dielectric film
22
and is patterned to make a mask. The dielectric film
22
is selectively etched by employing the mask to form a wiring trench
24
therein and the photoresist film is removed (FIG.
1
D).
A metal film of a low electric resistance made of, for example, aluminum or copper is then deposited on the dielectric film
22
including the side wall and the bottom wall of the wiring trench
24
, and the metal film on the dielectric film
22
is removed to leave an embedded wiring
26
having a single damascenel structure (FIG.
1
E).
When, however, the embedded wiring having the single damascenel structure is formed in accordance with the conventional method as described above, an imprecise positional alignment is liable to occur between the via plug and the wiring trench. As a result, deficiencies in electrical connection may be generated between the via plug and the wiring trench. This problem is more remarkable when a so-called border-less via structure is formed in which the width of an embedded wiring is reduced as narrow as to that of a via plug for miniaturization and high integration of semiconductor devices.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide an embedded wiring of a single damascenel structure having a high reliability in electrical connection, and a method for forming the same.
The present invention provides, in a first aspect, an embedded wiring structure comprising: a substrate; a first wiring layer, a first interlayer dielectric film, an etch-stop layer and a second interlayer dielectric film having therein a wiring trench consecutively formed to overlie the substrate; a via plug penetrating the second interlayer dielectric film, the etch-stop layer and the first interlayer dielectric film to reach the first wiring layer; and a second wiring layer embedded in the wiring trench and in contact with an upper side wall of the via plug.
The present invention provides, in a second aspect, a method for forming an embedded wiring structure comprising the steps of: forming a first wiring layer overlying a substrate; sequentially forming a first interlayer dielectric film, an etch-stop layer and a second interlayer dielectric film on the first wiring layer; forming a via hole penetrating the second interlayer dielectric film, the etch-stop layer and the first interlayer dielectric film to reach the first wiring layer; forming a via plug in the via hole; patterning the second interlayer dielectric film to form a wiring trench which exposes an upper side wall of the via plug; and forming a second wiring layer in contact with an upper side wall of the contact plug.
In accordance with the present invention, since the embedded wiring and the via plug are in contact with each other with a relatively large surface area, deficiencies in electrical connection are hardly generated, and reliability in the electrical connection is significantly higher than that of a conventional connection structure.
Especially effective performance can be obtained in the present invention if the wiring trench and the via plug have the same width.
A low electric resistance metal which may be employed in the metal film in the present invention includes and is not restricted to aluminum and copper. An alloy including one of these metals can be also employed.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 5854515 (1998-12-01), Bandypopadhyay et al.
patent: 5925933 (1999-07-01), Colgan et al.
patent: 5935515 (1999-08-01), Fang et al.
patent: 6110826 (2000-08-01), Lou et al.
patent: 8-201399 (1996-08-01), None
patent: 8-213459 (1996-08-01), None
patent: 8-316309 (1996-11-01), None
patent: 8-335634 (1996-12-01), None
patent: 10-199972 (1998-07-01), None
patent: 10-199974 (1998-07-01), None
Clark Sheila V.
Rosenman & Colin LLP
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