Embedded system with reduced susceptibility to single event...

Details Embedded system with reduced susceptibility to single event... Embedded system with reduced susceptibility to single event...

2008-01-29

2008-01-29

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

10940919

ABSTRACT:
An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a non-volatile memory that can store a copy of the at least one instruction set, and a data memory that can store at least one data sequence. The data memory utilizes an error correction coding (ECC) scheme. A controller, which is responsive to the instruction memory, the non-volatile memory, and the data memory, replaces the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory, if a parity error is detected in connection with the at least one instruction set in the instruction memory. The controller also operates in conjunction with the data memory to implement the ECC scheme.

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Internet cite, www.cisco.com/warp/public/779/largeent/learn/technologies/ina/IncreasingNetworkAvailability-FAQ.pdf, “Frequently Asked Questions on Single Event Upsets (SEU) and Error Correcting Codes (ECC)”, Prior to Sep. 14, 2004, pp. 1-5.

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