Embedded system and interruption handling method

Details Embedded system and interruption handling method Embedded system and interruption handling method

2011-03-22

2011-03-22

Cleary, Thomas J (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Programmable interrupt processing

C710S260000, C710S265000, C710S269000

Reexamination Certificate

active

07913017

ABSTRACT:
An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine.

REFERENCES:
patent: 5381552 (1995-01-01), Dahlberg et al.
patent: 6654839 (2003-11-01), Hashimoto
patent: 2002/0016880 (2002-02-01), Bhagat
patent: 2003/0074508 (2003-04-01), Uhler
patent: 2006/0064528 (2006-03-01), Soltis et al.

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