Embedded symmetric multiprocessor system debug

Details Embedded symmetric multiprocessor system debug Embedded symmetric multiprocessor system debug

2006-03-07

2006-03-07

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S727000, C714S724000, C324S763010, C324S765010

Reexamination Certificate

active

07010722

ABSTRACT:
A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and debug slave signals to debug slave central processing units. An executive master test access port controller responds to the external test signals and controls the test signal multiplexer. A control register loadable via the executive master test access port stores the debug slave signals. A test data output multiplexer connects the test data output line of the selected debug master central processor unit to an external test data output line. The external test signals includes a debug state signal supplied to each central processing unit. This selects either a normal mode or a debug mode at each central processor unit.

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