Embedded substrate interconnect for underside contact to...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S387000, C257S401000

Reexamination Certificate

active

07573101

ABSTRACT:
A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

REFERENCES:
patent: 5350708 (1994-09-01), Yagishita et al.
patent: 5352923 (1994-10-01), Boyd et al.
patent: 5610099 (1997-03-01), Stevens et al.
patent: 5827762 (1998-10-01), Bashir et al.
patent: 6140674 (2000-10-01), Hause et al.
patent: 6407427 (2002-06-01), Oh
patent: 6580137 (2003-06-01), Parke
patent: 6759282 (2004-07-01), Campbell et al.
patent: 6838332 (2005-01-01), Sanchez et al.
patent: 6891263 (2005-05-01), Hiramatsu et al.

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