Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-06-21
2002-05-21
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C029S593000
Reexamination Certificate
active
06391669
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of multilayer substrates, and more particularly pertains to the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, the invention is directed to the provision of embedded structures in a multilayer substrate, such as employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.
The invention is further directed to the provision of a novel method for the non-destructive testing of electrical integrity in multilayer devices and substrates, as well as implementing electrical testing for via to via alignment and interface layer alignment in multilayer substrates and electrical semiconductor devices, such as are employed in chip carrier packaging.
During the process for the building-up or fabricating of multilayer ceramic substrates there are produced critical electrical interfaces which exist on each layer and also between adjacent or superimposed layers. These interfaces are typically formed on dielectric layers known as greensheets and constitute vias and electrically conductive patterned features such as lines or mesh planes, each of which may have a capture pad or cap provided on their ends in order to increase the contact area with their respective adjoining electrically conductive circuit element. The alignment of each of these interfaces is extremely critical, especially inasmuch as ever narrower line widths and smaller vias are used to be able to increase the wiring density of an electrical device. Also, at high frequencies above 10 GHz, discontinuities in conductor surface features can degrade the electrical performance of signals. Misaligned conductor interfaces can act as such discontinuities and limit the high frequency performance of multilayer devices. Typical specifications permit no more than one-half the diameter of a via as the misregistration or offset between adjacent layers at any location within a laminate. After adjacent layers are laminated the misregistration is practically impossible to quantify within any laminate, unless slow and expensive x-ray tooling is utilized or more accurately if destructive analyses, such as cross-sectioning, are performed on the laminate. This is a time-consuming procedure and provides information concerning alignment between adjacent layers with regard to only a very small area of the substrate. Similarly, when any substrates are made on a single multilayer laminate the traceability of a substrate or of such type of electrical device, which has been found to be defective due to interlayer misalignment, back to the parent laminate is very difficult when serialization of each substrate on each laminate is not employed. Moreover, inasmuch as the laminate may have been subject to poor alignment of the layers in only one corner or small region thereof, not all parts may be defective, and some may be good. By the same account, a substrate or device which has been cross-sectioned and found to possess a good alignment between layers from the center of the laminate may provide false information since devices formed from the corners of the same laminate will typically be subjected to the greatest degree of misalignment from a layer which is slightly rotated during stack-up or lamination within the laminate.
There are also times during processing of cofired multilayer ceramic substrates when shrinkage mismatches between dielectric and conductor features particularly at line to via connections become distorted. This can produce electrical connections which can cause risks of electrical failure during thermal cycling due to CTE (coefficient of thermal expansion) mismatches between the dielectric and conductor.
In actual practice, proper alignment and complete area overlap at these interlayer interfaces is desired; however in reality, there is frequently encountered layer-to-layer misalignment due to greensheet movement during deposition of metallized features, often as organic based pastes, drying, handling, stacking, among other fabrication steps. Similarly, incomplete paste deposition can result in poor via fill. All of these factors can result in partial interlayer overlap with the potential for thermal expansion driven conductor-to-conductor electrical interface failure. This failure mode can be encountered with ceramic substrates when copper metallization, which has a very high coefficient of thermal expansion compared to most ceramics, is stressed during thermal cycling, fails and causes an electrical open. Severe conductor to via or inter layer via misalignment may also result in electrical shorting between metallized features. Likewise failures can be caused by manufacturing process violation of minimum feature separation requirements which may be required to ensure optimum electrical performance. Presently, there are no simple, reliable tests available for non-destructive detection as spacing violations in laminated parts. High-resistance shorts between metallized features can also influence the electrical performance of a semiconductor or electronic package. Ideally, there should be available a method to quickly and non-destructively determine whether an individual device, such as that resulting from the singulation of a multi-up laminate, has good alignment so as to provide an early screening for these types of defects.
2. Discussion of the Prior Art
Although various devices and methods have been developed in the technology for implementing the testing of the electrical integrity of semiconductor devices, particularly such as those which employ multilayer substrates possessing electrical interfaces, and which have electrical devices arranged on the surfaces thereof, including the testing of via to via alignment and layer interface alignment, these are primarily limited in scope and also fail to provide for the desirable kinds of non-destructive testing of these substrates and devices. Fulford, Jr. et al. U.S. Pat. No. 5,916,715 pertains to a process utilizing lithographically deposited metallized features in order to determine the layer alignment of these features for a multilayer substrate of a device. Each and every layer of the multilayer device requires multiple metallized features in order to provide a determination as to whether alignment is obtained within a specified range of microns. The testing which is implemented through the intermediary of this process is not employable for thick film alignment assessments inasmuch as it consumes considerable space on every greensheet layer during processing.
Hanson U.S. Pat. No. 5,863,446 describes an electrical arrangement for extracting layer to layer registration, wherein an alignment test feature is employed in an organic laminate for an electrical device. Resistors are positioned at strategic surface locations in order to determine lateral alignment of laser drilled conductive vias, such vias being produced in laminates requiring precise control of laser energy so as not to pierce the resistive layer which will be employed in order to assess the degree of misregistration, and necessitating precise placement of vias. It is difficult to produce laser holes in a fired ceramic substrate, and even more complex to be able to stop at a buried resistive layer and to subsequently metallize this via to a surface pad which can be probed for electrical integrity.
Lee et al. U.S. Pat. No. 5,756,146 discloses a method which permits optical inspection of metal lines in or on a transparent substrate. To the contrary, ceramic substrates, as well as most high performance chip carriers are not transparent and thus neither a laminated or sintered substrate as employed in the present construction would be suitable for the type of inspection testing disclosed in this
Fasano Benjamin V.
Longworth Hai P.
Peterson, III Vincent P.
Plachy Anthony L.
Wiggin Robert N.
International Business Machines - Corporation
Nguyen Tuan H.
Pepper Margaret A.
Pert Evan
Scully Scott Murphy & Presser
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