Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2011-06-14
2011-06-14
Arbes, C. J (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S825000, C029S830000, C029S840000, C029S852000, C438S238000, C438S381000
Reexamination Certificate
active
07958626
ABSTRACT:
A method of forming an embedded passive component network substrate includes providing a first carrier with a first dielectric layer and patterning the first dielectric layer to form a first patterned dielectric layer including circuit pattern artifacts. A first etch stop layer is plated within the circuit pattern artifacts. A first conductor layer is plated on the first etch stop layer and within the circuit pattern artifacts. The first etch stop layer and the first conductor layer form a first etch stop metal protected circuit pattern comprising a passive component embedded with the first patterned dielectric layer.
REFERENCES:
patent: 3698821 (1972-10-01), Ekstrand
patent: 4194127 (1980-03-01), Schmidt
patent: 4776022 (1988-10-01), Fox et al.
patent: 5108541 (1992-04-01), Schneider et al.
patent: 5116459 (1992-05-01), Kordus et al.
patent: 5181445 (1993-01-01), Cothrell
patent: 5232505 (1993-08-01), Novak et al.
patent: 5338900 (1994-08-01), Schneider et al.
patent: 5369431 (1994-11-01), Levy et al.
patent: 5506793 (1996-04-01), Straayer et al.
patent: 5517234 (1996-05-01), Gerber et al.
patent: 5784484 (1998-07-01), Umezawa
patent: 5946569 (1999-08-01), Huang
patent: 6021380 (2000-02-01), Fredriksen et al.
patent: 6035527 (2000-03-01), Tamm
patent: 6091075 (2000-07-01), Shibata et al.
patent: 6194250 (2001-02-01), Melton et al.
patent: 6303423 (2001-10-01), Lin
patent: 6462107 (2002-10-01), Sinclair et al.
patent: 6476388 (2002-11-01), Nakagaki et al.
patent: 6603877 (2003-08-01), Bishop
patent: 6730857 (2004-05-01), Konrad et al.
patent: 6740964 (2004-05-01), Sasaki
patent: 6869870 (2005-03-01), Lin
patent: 6872591 (2005-03-01), Wang et al.
patent: 6919514 (2005-07-01), Konrad et al.
patent: 7242081 (2007-07-01), Lee
patent: 7335571 (2008-02-01), Rumsey et al.
patent: 7345361 (2008-03-01), Mallik et al.
patent: 7372151 (2008-05-01), Fan et al.
patent: 7384864 (2008-06-01), Lin
patent: 7396756 (2008-07-01), Lin
patent: 7420276 (2008-09-01), Lin et al.
patent: 7553738 (2009-06-01), Min et al.
patent: 7714996 (2010-05-01), Yan et al.
patent: 7741698 (2010-06-01), Chinthakindi et al.
patent: 7763954 (2010-07-01), Chinthakindi et al.
patent: 2001/0017694 (2001-08-01), Oomori et al.
patent: 2003/0076666 (2003-04-01), Daeche et al.
patent: 2004/0021201 (2004-02-01), Ballantine et al.
patent: 2004/0043551 (2004-03-01), Beroz
patent: 2004/0104417 (2004-06-01), Song et al.
patent: 2004/0120570 (2004-06-01), Levi et al.
patent: 2004/0183094 (2004-09-01), Caletka et al.
patent: 2004/0239918 (2004-12-01), Sugihara et al.
patent: 2005/0116337 (2005-06-01), Chua et al.
patent: 2005/0194533 (2005-09-01), Okuda et al.
patent: 2006/0124874 (2006-06-01), Uto et al.
patent: 2007/0206267 (2007-09-01), Tung et al.
patent: 2007/0273014 (2007-11-01), Lee et al.
patent: 2007/0273049 (2007-11-01), Khan et al.
patent: 2007/0290376 (2007-12-01), Zhao et al.
patent: 2008/0003414 (2008-01-01), Magera et al.
patent: 2008/0122079 (2008-05-01), Chen et al.
patent: 2008/0136041 (2008-06-01), Kotake et al.
patent: 2008/0225283 (2008-09-01), Chi et al.
patent: 2008/0230887 (2008-09-01), Sun et al.
patent: 2009/0229856 (2009-09-01), Fredenberg et al.
Berry et al., “Thin Stacked Interposer Package”, U.S. Appl. No. 11/865,617, filed Oct. 1, 2007.
Scanlan, “Package-on-package (PoP) with Through-mold Vias”,Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation.
Kim et al., “Application of Through Mold Via (TMV) as PoP base package”,58thECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE.
Huemoeller et al., U.S. Appl. No. 11/765,806, filed Jun. 20, 2007, entitled “Metal Etch Stop Fabrication Method and Structure”.
Huemoeller et al., U.S. Appl. No. 11/765,828, filed Jun. 20, 2007, entitled “Embedded Die Metal Etch Stop Fabrication Method and Structure”.
Huemoeller Ronald Patrick
Karim Nozad
Rusli Sukianto
Amkor Technology Inc.
Arbes C. J
Gunnison McKay & Hodgson, L.L.P.
Hodgson Serge J.
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