Embedded memory control circuit for control of access operations

Details Embedded memory control circuit for control of access operations Embedded memory control circuit for control of access operations

1999-05-27

2000-10-24

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, G11C 800

Patent

active

061377457

ABSTRACT:
An embedded memory control circuit is provided for use with a memory module consisting of a number of partly-defective memory chips to allow these partly-defective memory chips to be combined for use as a single memory unit with the same address space of each nondefective memory chip. The embedded memory control circuit includes a bank-select unit, a bank-suppress unit, and a data output buffer. The bank-select unit is capable of detecting whether each of the banks in the memory module is defective or nondefective to thereby generate a plurality of corresponding bank-status signals each indicative of whether the corresponding bank is defective or nondefective. The bank-suppress unit is capable of, in response to the bank-status signals and the bank-select signal, generating a plurality of defective-bank suppressing signals which can suppress each defective bank in the memory module, if any. The data output buffer is capable of, in response to the defective-bank suppressing signals from the bank-suppress unit, performing an access operation to the memory module with all the defective banks, if any, being suppressed by the defective-bank suppressing signals.

REFERENCES:
patent: 5398206 (1995-03-01), Akizawa et al.
patent: 5528539 (1996-06-01), Ong et al.

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