Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-12-04
2001-07-03
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S006130, C714S042000
Reexamination Certificate
active
06256756
ABSTRACT:
BACKGROUND
The present invention concerns integrated circuits and pertains particularly to an improved memory bank system which increases manufacturing component yield.
Many integrated circuits (components) have embedded memory cells used for the storage of information. When manufacturing components which have embedded memory, defects in the memory cells make the memory cell unusable. If the memory errors caused by the defects are uncorrected, the entire component is unusable, and the overall manufacturing yield is reduced.
A typical memory contains multiple blocks (“banks”). Each block contains many memory cells. Each memory cell normally contains a single bit of data, although some technology permits more than one bit of data per memory cell. As the size of the memory gets larger there is an increased chance that there is an error in a memory cell. For example, if P(G) is the probability of a memory bit being good, then the probability of zero errors in a memory of n bits is P(G)
n
.
For example, if P(G)=0.99 and there are 100 memory cells, the probability of zero errors is 0.99
100
which is approximately equal to 0.37. Thus, the probability of zero errors in a large memory can be very, very small.
There are several techniques for working around bit errors in memory, thus increasing the yield of components with embedded memory.
For example, memory bank remapping can be performed. In this method, the manufacturers build in additional spare blocks of memory. When the memory is manufactured, all memory blocks are tested. If a memory block has any bit errors, the block is mapped out and one of the spare blocks is mapped into its place. Often called “self-repair”, this remapping is done by disconnecting the failed memory block and rewiring a spare memory block into its place. If there are no bit errors, the spare memory blocks are unused. If there are more blocks with bit errors than there are spare blocks, the entire component cannot be used, and the yield is reduced. However, generally memory bank remapping is costly and cumbersome to implement.
Another technique used to increase the yield of components with embedded memory is the use of error correcting memory. Although many variants exist, each word of error correcting memory typically has 12 memory cells which hold the data and the error correction bits. An error-correction function is applied to the data and error correction code, yielding an 8 bit result. The error correction function is typically able to correct a single bit error, and detect 2 bit errors. Because of its high additional cost, error correcting memory is used primarily in mission-critical systems where very high reliability is required. Error correcting memory is not a low cost method of increasing yield.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a component with embedded memory is manufactured. The component includes a plurality of memory buffers and a processor. The size of these memory buffers can be determined independently of the size of the memory banks. During self-test of the component, the processor performs testing of the plurality of memory buffers in order to detect bad memory locations. The processor places into a free buffer list pointers to memory buffers from the plurality of memory buffers for which no bad memory locations have been detected.
In the preferred embodiment, the processor identifies in an error log memory buffers in which bad memory locations have been detected. For example, the error log is stored in non-volatile memory. This allows the error log to permanently identify memory buffers in which bad memory locations were detected during testing which was performed as part of a manufacturing process of the component as well as by the processor during component self test.
During normal operation of the component, a buffer manager accesses the free buffer list to determine which memory buffers are currently available. Entities within the component make requests for memory buffers to the buffer manager. For example, the component is a network switch and the entities are each a switch port.
The present invention has significant advantages over prior art solutions. For example, the present invention is superior to the practice of mapping out defective memory blocks (also called bank swapping), for example, because no internal “rewiring” is needed to swap a good block in place of a defective block. Additionally, in embodiments of the present invention there is no performance delay, which is often the case with the bank swapping mechanisms.
With bank swapping, the spare memory banks are unavailable unless they are swapped into the place of a defective memory block. The present invention allows all good blocks of memory to be used, which increases efficiency.
Another advantage of the described embodiments of the present invention over solutions which map out defective blocks is that for embodiments of the present invention the block size and number of spare blocks need not be constrained by the physical memory organization. For example, a single large embedded memory can be used, or multiple smaller memories can be used. The block size can be any size, as long as there is enough room in the free buffer list. With bank swapping, the spare blocks must be tightly associated with the blocks they can replace. If a spare block is not tightly coupled with the block it replaces, a significant performance degradation will occur because of the extra circuitry needed and physical distance between the spare block and the block it replaces.
Additionally, the disclosed embodiments of the invention provide a higher level of system reliability over systems which use bank swapping. In described embodiments of the present invention, when faults are detected after manufacture, these faults can be permanently logged. Thus, intermittent faults are more likely to be detected.
The present invention is also superior to those prior art solutions which use error correcting memory. Error correcting memory typically requires the addition of 4 extra bits for every 8 bits of memory resulting in a greater than 50% increase in memory component size. Additionally, error correcting memory has higher latency because additional processing must be done for each of the bits read from memory before the data is passed on to other modules in the system. Because of its high cost, error correcting memory is used to increase system reliability, and is not generally considered as a solution to increasing yield.
REFERENCES:
patent: 5077737 (1991-12-01), Leger et al.
patent: 5105425 (1992-04-01), Brewer
patent: 5862314 (1999-01-01), Jeddeloh
patent: 6088817 (2000-07-01), Haulin
Hewlett--Packard Company
Tu Christine T.
LandOfFree
Embedded memory bank system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Embedded memory bank system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Embedded memory bank system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2437006