Embedded frame buffer system and synchronization method

Details Embedded frame buffer system and synchronization method Embedded frame buffer system and synchronization method

1999-12-07

2000-10-03

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345519, 345509, 713400, 713500, G06F 1516

Patent

active

061280259

ABSTRACT:
A multiple embedded memory frame buffer system includes a master graphics subsystem and a plurality of slave graphics subsystems. Each subsystem includes a frame buffer and a color palette for decompressing data in the frame buffer. The master subsystem further includes a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device. The system further includes a timing system for determining which outputs of the subsystems are to to be converted by the digital to analog converter at a given time. A method of synchronization of embedded frame buffers for data transfer through a single output includes the steps of generating a first clock signal and a second clock signal in a master embedded frame buffer, sending the first and second clock signals to a slave embedded frame buffer and delaying the second clock signal to be in phase with a third clock signal generated by a graphics controller such that no data is lost when transferring data from the master and slave embedded frame buffers.

REFERENCES:
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patent: 4562435 (1985-12-01), McDonough et al.
patent: 5608418 (1997-03-01), McNally
patent: 5608427 (1997-03-01), Hoffert et al.
patent: 5712664 (1998-01-01), Reddy
patent: 5757338 (1998-05-01), Bassetti et al.
patent: 5887272 (1999-03-01), Sartore et al.

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