Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent
1998-06-30
1999-10-05
Nelms, David
Static information storage and retrieval
Read/write circuit
Simultaneous operations
365203, 711137, G11C 1604
Patent
active
059634812
ABSTRACT:
An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.
REFERENCES:
patent: 4577293 (1986-03-01), Matick et al.
patent: 4608666 (1986-08-01), Uchida
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4794559 (1988-12-01), Greeberger
patent: 4870622 (1989-09-01), Aria et al.
patent: 4894770 (1990-01-01), Ward et al.
patent: 4926385 (1990-05-01), Fujishima et al.
patent: 4943944 (1990-07-01), Sakui et al.
patent: 5025421 (1991-06-01), Cho
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5134616 (1992-07-01), Barth, Jr. et al.
patent: 5148346 (1992-09-01), Naab et al.
patent: 5179687 (1993-01-01), Hidaka et al.
patent: 5184320 (1993-02-01), Dye
patent: 5184325 (1993-02-01), Lipovski
patent: 5214610 (1993-05-01), Houston
patent: 5226009 (1993-07-01), Arimoto
patent: 5226139 (1993-07-01), Fujishima et al.
patent: 5226147 (1993-07-01), Fujishima et al.
patent: 5249282 (1993-09-01), Segers
patent: 5305280 (1994-04-01), Hayano
patent: 5329489 (1994-07-01), Diefendorff
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5359722 (1994-10-01), Chan et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5390308 (1995-02-01), Ware et al.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5471601 (1995-11-01), Gonzales
patent: 5539696 (1996-07-01), Patel
patent: 5566318 (1996-10-01), Joseph
patent: 5568427 (1996-10-01), Takemae
patent: 5600605 (1997-02-01), Schaefer
patent: 5627791 (1997-05-01), Wright et al.
patent: 5636173 (1997-06-01), Schaefer
patent: 5655105 (1997-08-01), McLaury
patent: 5666321 (1997-09-01), Schaefer
patent: 5673233 (1997-09-01), Wright et al.
patent: 5761695 (1998-06-01), Maeda et al.
patent: 5778436 (1998-07-01), Kedem et al.
"DM 2202 EDRAM 1Mb x 4 Enhanced Dynamic RAM--Product Review," May 22, 1991, Ramtron, Colorado Springs, Colorado.
Sartore, "New Generation of Fast Enhanced DRAMS Replace Static RAM Caches in High-end PC Work Station" 1991.
Niijima et al, "QRAM--Quick Access Memory System", IEEE International Conference, pp. 417-420, Sep. 17, 1990.
Bursky, "Combination DRAM-SRAM Removes Secondary Caches", Electr. Design, vol. 40, No. 2, pp. 39-43, Jan. 23, 1992.
Goodman et al. "Use of Static Column RAM as a Memory Hierachy," 11.sup.th Annual Symposium, IEEE, 1984, pp. 167-174.
Ohta et al., "A 1 MB DRAM with 33 MHz Serial I/O Ports" Digest of Technical Papers, 1986 IEEE, pp. 274-275 (1986).
Hitachi, "Multiport Video RAM, " Specification for parts HM53461 and HM 53462, pp. 30-33.
Dosaka et al., "A 100MHz 4Mb Cache DRAM with Fast Copy-back Scheme," Digest of Technical Papers, 1992 IEEE International Solid-State Circuits Conference, pp. 148-149 (Jun. 1992).
Micron Technical Note TN-04-21, "Reduce Cycle Times with Extended Data Out", Mar. 1993.
Alwais Michael
Peters Michael
Enhanced Memory Systems Inc.
Kelly, Esq. Robert
Kubida, Esq. William J.
Lam David
Nelms David
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