Embedded DRAM with bias-independent capacitance

Details Embedded DRAM with bias-independent capacitance Embedded DRAM with bias-independent capacitance

2011-04-19

2011-04-19

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S149000, C365S230060

Reexamination Certificate

active

07929359

ABSTRACT:
An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.

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