Embedded DRAM cache memory and method having reduced latency

Details Embedded DRAM cache memory and method having reduced latency Embedded DRAM cache memory and method having reduced latency

2007-03-06

2007-03-06

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000, C711S144000, C711S145000

Reexamination Certificate

active

10932473

ABSTRACT:
A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system controller includes a system memory controller coupled to the system memory, a processor interface coupled to the processor and an embedded cache memory integrated with the memory controller and the processor interface. The cache memory includes at least one DRAM array, at least one tag memory, and at least one cache memory controller. The cache memory controller initiates an access to either or both the DRAM array and the tag memory, as well as the system memory, before the cache memory controller has determined if the access will result in a cache hit or a cache miss. If the cache memory controller determines that the access will result in a cache hit, data are coupled from the DRAM array to the processor. If the cache memory controller determines that the access will result in a cache miss, data are coupled from the system memory to the processor.

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