Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-06-30
2002-02-12
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S678000, C257S916000, C361S306200, C361S306300
Reexamination Certificate
active
06346743
ABSTRACT:
FIELD
The present invention relates to integrated circuit packaging and, more particularly, to a package assembly for integrated circuits, electrical system hardware, and computer systems, although not limited thereto.
BACKGROUND
Recent developments in integrated circuit technologies have led to higher levels of performance and faster operation speeds and, also, have led to the development of more complex integrated circuits (ICs). These and other achievements and increased levels of complexity has made it more and more difficult to maintain the power source level applied to an integrated circuit (IC) within a prescribed range. For example, technological achievements in integrated circuit technologies and, especially, in the design of processors have driven the operating frequencies (e.g., clocking speeds) to much higher levels (e.g., the high end of the megahertz [MHz] range) and, correspondingly, are driving voltages as well as noise margins lower and lower.
Typically, in integrated circuit (IC) packages such as for mounting processor dies, among other integrated circuitry, a voltage regulator circuit is used to provide a steady DC voltage. This is irrespective of whether such DC power is from a battery or has been converted from alternating current (AC) power. A known way of providing voltage regulation to a semiconductor die or IC chip is mounting a voltage regulator module (VRM) on the PC board (or motherboard), for example, of a computer system. VRMs, however, are typically ineffective in meeting the power distribution system (PDS) target impedance of ICs at operating frequencies beyond the low end of the kHz range. As a result, therefore, as frequencies and edge rates of ICs and, especially, of high performance processors have escalated greatly, bypass capacitors operating as power decouplers have been utilized to reduce the system noise as well as suppressing unwanted radiation. Extensive discussion regarding the characteristics of a power distribution system (PDS) and use of ceramic capacitors in high speed ICs is given in the published article, entitled “Power Distribution System Methodology and Capacitor Selection for Modem CMOS Technology,” L. D. Smith et al., in IEEE Transactions on Advance Packaging, Vol. 22, No. 3, pp. 284-291, August 1999.
In order to provide effective power decoupling capacitors for the next generation of integrated circuits including single chip processors and microcomputers, although not limited thereto, there will be a need for bypass capacitors integrated into the interconnect substrate, for example, a processor die interconnect substrate.
With the development of chip capacitors and vias (and microvias) technology, the embedding of discrete capacitor elements such as multiterminal pair ceramic capacitors has now been made possible. However, the connection of such capacitors leads to inductive noise from the wirings and loops developed by the presence of the vias and various wiring layers electrically connected thereto, including the supply and ground wirings (or power and ground planes). These inductances can adversely affect the PDS performance, especially, at high frequencies and should be taken into account when considering reducing the system noise attributed, for example, to the switching on of power as well as during the actual running of the die or chip circuitry. Therefore, in addition to placing the capacitors inside the processor interconnect substrate or, for example, in any IC package, printed circuit board (PCB) or, for that matter, in the core layer of a motherboard on which high performance semiconductor integrated circuits are mounted, the connection assembly of such embedded capacitors must be such as to maintain the effective inductance resulting from the placement thereof to a sufficiently low level so that a low power distribution system (PDS) impedance is achieved even at frequencies (or clocking speeds) at high ends of the megahertz (MHz) range and beyond.
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L. D. Smith et al., “Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology”, IEEE Transactions on Advanced Packaging, vol. 22, No. 3, Aug. 1999, pp. 284-291.
R. Shukla et al., “Flip Chip CPU Package Technology at Intel: a Technology and Manufacturing Overview”, 1999 Electronic Components and Technology Conference, Jun. 1999, pp. 945-949.
V. K. Nagesh et al., “Challenges of Flip Chip on Organic Substrate Assembly Technology”, 1999 Electronic Components and Technology Conference, Jun. 1999, pp. 975-978.
J. Darnauer et al., “Electrical Evaluation of Flip-Chip Package Alternatives for Next Generation Microprocessors”, IEEE Transactions on Advanced Packaging, vol. 22, No. 3, Aug., 1999, pp. 407-415.
Chung Chee-Yee
Figueroa David G.
Li Yuan-Liang
Antonelli Terry Stout & Kraus LLP
Clark Jhihan B
Intel Corp.
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