Elmore model enhancement

Details Elmore model enhancement Elmore model enhancement

2001-01-26

2003-04-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06543038

ABSTRACT:

BACKGROUND
This invention generally relates to the Elmore Model, and more specifically relates to an enhancement to the Elmore Model so that wire delays can be more accurately estimated.
The Elmore Model is a mathematical model which is used to estimate the delays at tapping points along a RC line. In other words, it is a tool for estimating the delay associated with providing a signal over a wire to a capacitive load. The Elmore Model is widely used in circuit design. For example, the Elmore Model is widely used during construction of a balanced clock tree (BCT) at different levels of clock net partition. The Elmore Model is described in several publications. For example, see W. C. Elmore, “The transient response of damped linear networks with particular regard to wide-band amplifier”, J Applied Physics, Vol. 19, no. 1, pp. 55-63, January 1948. Generally, one having ordinary skill the art is very familiar with the Elmore Model.
While the Elmore Model is a helpful model to use for wire delay estimations, the Elmore Model is not perfect, and very often introduces some error. In other words, the actual or real delay is often different than the delay as calculated using the Elmore Model. This error may be compounded when attempting to calculate skew using the Elmore Model, where one delay calculation is compared to another. Obviously, if the Elmore Model were to be improved or enhanced, estimations using the Elmore Model would be more accurate. This would improve designs. For example, if the Elmore Model were to be improved or enhanced, clock skew can be minimized among partition groups in a balanced clock tree (BCT).
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide an enhancement to the Elmore Model.
Another object of an embodiment of the present invention is to counter or compensate for errors which would otherwise be introduced using the Elmore Model.
Still another object of an embodiment of the present invention is to provide a method of more accurately estimating delays using the Elmore Model.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a method for calculating skew associated with providing a signal to a capacitive load along a first and second wire. The method includes steps of calculating a skew error which would result if the Elmore Model were used to calculate delays using the actual length of the wires, calculating a new effective length for the second wire based on the error which has been calculated, using the Elmore Model to calculate an effective delay which would be associated with providing the signal to the capacitive load along the new effective length of wire, and calculating skew using the effective delay which has been calculated. Preferably, the new effective length for the second wire is calculated by considering the actual lengths of the first and second wires, the capacitance of a unit length of wire and the capacitance of the capacitive load. More specifically, preferably the following formula is used:
 &Dgr;
l
2
=−(
L
o
/2
+l
2
)+(L
o
2
/4+1.4
l
2
2
+0.4
L
o
l
2
−0.4
l
1
2
+0.6
L
o
l
1
)
½
wherein
&Dgr;l
2
is an amount added to the actual length of the second wire to arrive at the new effective length, L
o
is the capacitance of the capacitive load divided by the capacitance of a unit length of wire, l
1
is the actual length of the first wire, and l
2
is the actual length of the second wire.
The method can be used, for example, to minimize clock skew among partition groups in a balanced clock tree (BCT).


REFERENCES:
patent: 6473890 (2002-10-01), Yasui et al.
Tsay, “An Exact Zero-Skew Clock Routing Algorithm”, IEEE, 1993.*
Chao et al. “Zero Skew Routing with Minimum Wirelength”, IEEE, 1992.*
Yoda et al, “Clock Scheduling with Consideration of Modification Cost in Semi-Syncronous Circuit.”, Technical Report of Institute of Electronics, Information and Communication Engineers, CAS99-36, pp. 45-52. 1999.

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