Elimination of SOI parasitic bipolar effect

Details Elimination of SOI parasitic bipolar effect Elimination of SOI parasitic bipolar effect

1998-11-12

2000-11-21

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 21, 326 26, 326 27, 326119, 326121, H03K 1716, H03K 19094

Patent

active

061508349

ABSTRACT:
The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.

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