Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-02-28
2001-06-26
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C205S645000, C205S662000, C216S088000, C216S085000, C438S008000, C438S745000
Reexamination Certificate
active
06251787
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of semiconductor fabrication. More particularly, the invention is a method for eliminating dissolution and/or corrosion of metallic conductors induced by light exposure of partially fabricated semiconductor devices.
2. Description of Related Art
In semiconductor device fabrication there is a constant need for methods to improve the reliability, yield and cost of fabrication while increasing feature density and decreasing feature size. One feature for which reliability is a great concern as its size decreases is the wiring that connects various devices on a chip. One method for creating this wiring is the damascene metal patterning processes. Today, the damascene process is used for a variety of wiring and contacts in semiconductor fabrication, replacing the more expensive traditional reactive ion etch (RIE) metal processing in products such as CMOS memory and logic.
Single damascene is defined as using the damascene process for global wiring and interconnects only. Dual damascene is where damascene wiring is combined with a damascene interconnect for even greater cost reduction.
The damascene metal process involves first etching a trench into a dielectric layer on a semiconductor wafer. The wafer is then covered with a conductor, this conductor filling the trench and covering the dielectric layer. The wafer is then polished, typically using a form of chemical mechanical polish (CMP), down to the dielectric layer. The dielectric layer, typically an oxide, is not as easily polished away by the CMP as the metal. Thus, the oxide serves as a “stop” for the polish process. The CMP leaves the conductor embedded as wires in the dielectric. This process can be used to create global wiring, interconnects, and contacts. The damascene process has been used extensively with tungsten or aluminum as the conductor and silicon dioxide as the dielectric.
As integrated circuit devices and the associated metal lines become smaller, the relatively low conductivity of the tungsten or aluminum begins to become an issue. Because of its better conductivity, copper is a desirable conductor in the damascene process as feature size shrinks. Accordingly, it is also desirable as a conductor in other processes for forming wiring, interconnects, and contacts. However, copper is more susceptible to corrosion than metals used previously, such as tungsten, and its corrosion presents a senous manufacturing problem. Corrosion leads to pitting, that adversely affects the electrical properties of the lines, and also leads to opens in lines. Generally, the CMP environment is corrosive to copper and other metals, so corrosion inhibitors are included with the CMP slurry to prevent unwanted corrosion of metal. Surprisingly, conventional inhibitors are at times ineffective in protecting copper. Also, it is expected that the problem will exist for other metals or alloys susceptible to corrosion that may replace copper in the future. Unless the source of the copper damage can be diagnosed and remedied, serious limitations might be placed on reducing feature size in integrated circuit devices, hampering improvements in device technology. Thus, it can be seen from the above discussion that it would be an improvement in the art to prevent damage to corrosion susceptible metals during fabrication of semiconductor devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides eliminating the exposure of PN junctions to light capable of invoking a photovoltaic effect thus preventing the electrochemical dissolution of metal components. The invention also provides prevention of this photo-driven dissolution by introducing inhibitors both for the oxidation reaction (electrochemical dissolution of metal) and for the accompanying reduction reaction that completes the circuit in the electrochemical cell formed in the CMP environment.
The invention provides implementation of a darkened enclosure, such as a box or curtains, for use on tools for wafer CMP, brush cleaning, unloading, and rinsing. Alternatively, illumination of the wafer can be limited to wavelengths of light that do not provide enough energy to promote any electrons in the PN junction from the valence band to the conduction band. If no conducting electrons are generated, then no current will be induced in the PN junction and no electrochemical reactions will occur.
The invention also provides use of an inhibitor in the CMP slurry and/or post-CMP water rinse. By using an inhibitor prior to exposure of PN junctions on the wafer to light, the electrochemical dissolution reaction may be prevented once a current is induced in the PN junction. In one embodiment, a blocking agent, such as a high molecular weight surfactant, is added to interfere with both the oxidation and reduction reactions.
In another embodiment, a poisoning agent is used to impede the reduction portion of the electrochemical cell.
It is an advantage of the present invention that electrolysis and the consequent dissolution of metal on semiconductor devices may be prevented.
It is a further advantage that the methods and apparatus of the present invention may be used individually or in combination for maximum effect.
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Edelstein Daniel C.
Horkans Wilma J.
Luce Stephen E.
Lustig Naftall E.
Pope Keith R.
International Business Machines - Corporation
Powell William
Schmeiser Olsen & Watts
Walter, Jr. Howard J.
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