Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-12-21
2003-10-28
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S524000, C438S528000
Reexamination Certificate
active
06638832
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to methods for manufacturing microelectronic devices and integrated circuits and, more particularly, to fabrication of large scale complementary metal oxide semiconductor (CMOS) integrated circuits (ICs), which contain reduced channel width transistors.
BACKGROUND OF THE INVENTION
Construction of CMOS integrated circuits generally begins with the fabrication of a semiconductor substrate surface of two different conductivity types. The semiconductor substrate surface is fabricated usually in the form of regions of n-conductivity type silicon adjacent to regions of p-conductivity type silicon (Si). In one form, such a surface could be a p-type substrate having a n-well or tub region formed therein. Thus, the p-channel devices are formed in the n-well and the n-channel devices are formed in the surface that remains p-conductivity type.
Due to technological advancement, semiconductor devices are scaling down in size. Meanwhile, individual transistors are scaling down both in channel length and in channel width. Devices having a width of 1 micron (&mgr;) or smaller are known as “narrow width” devices. An example of a wide device is one having a width of 10&mgr;.
A problem for narrow width devices is control of threshold voltage (V
t
). Typically, the threshold voltage either strongly increases or decreases between wide devices and narrow width devices. This change in V
t
, can create problems. For example, a high V
t
can decrease transistor drive current causing slow performance. Also, a low V
t
can cause source-drain leakage current. Thus, it would be desirable to be able to maintain a constant V
t
over various transistor channel widths.
Germanium implantation has been used to change field isolation characteristics. For further information, the reader is directed to, e.g., U.S. Pat. No. 4,728,619 to Pfiester et al., the contents of which are incorporated herein by reference in their entirety. The Pfiester patent discloses using germanium implantation as a channel stop to increase field oxide threshold voltage. A high energy implant is done prior to field oxide growth to retard movement of the dopant, particularly boron, during subsequent integrated circuit fabrication processing.
What is needed is a method for controlling transistor device characteristics to maintain a near constant threshold voltage over a range of transistor channel widths, particularly as the transistor channel width drops below 0.5 microns.
SUMMARY OF THE INVENTION
The present invention provides control of threshold voltage (V
t
) for metal oxide semiconductor (MOS) transistors over a wide range of transistor device widths. Degradation of threshold voltage levels for transistors having small channel widths is prevented.
Briefly, after forming an isolation region separating transistors, the present invention employs a shallow, high dose blanket germanium implantation. The process of the present invention can employ a low-energy germanium (Ge) implant and is suitable for MOS transistors formed using local oxide isolation or shallow trench isolation techniques. Threshold voltage (V
t
) can be controlled to be a nearly constant value for transistors having large or small device features. Changes in semiconductor device processing can include a Ge implantation and a low temperature anneal.
The present invention, in one embodiment, sets forth a method for fabricating a metal oxide semiconductor (MOS) structure that controls threshold voltage V
t
in the structure, the method including generating an isolation region of the semiconductor structure on a major surface of a silicon substrate, implanting a germanium or other large diameter neutral conductivity type ion into the major surface of the semiconductor structure, annealing the semiconductor structure having the germanium ion implanted therein, and processing the semiconductor structure to create MOS devices having a near constant threshold voltage over a range of device channel widths.
In one embodiment of the invention, prior to the implanting step, the method can include growing a thin oxide on the major surface of the semiconductor structure. In another embodiment of the present invention, implanting includes implanting a dosage of between 1E14 and 1E16 per centimeter squared.
In yet another embodiment of the present invention, implanting includes blanket implanting to a depth of between 200 and 1,000A.
In another embodiment, the annealing includes annealing in a furnace or in a rapid thermal processing (RTP) tool.
In an example embodiment, annealing includes annealing out implant damage at a temperature of between 800 and 950° C. for between 15 and 45 minutes.
In another embodiment, the MOS devices are formed using local oxide isolation.
In an embodiment of the present invention, the MOS devices are formed using shallow trench isolation techniques.
In another, the range of the device channel widths is between 1.0&mgr; and 10.0&mgr;, inclusively.
In another embodiment of the invention, the range of the device channel widths is less than or equal to 1.0&mgr; and greater than zero.
In another embodiment, the device channel widths are less than or equal to 0.5&mgr; and greater than zero.
In another embodiment, the thin oxide layer is 200A thick or less and greater than zero.
In one embodiment of the invention, a metal oxide semiconductor (MOS) structure is disclosed featuring a Si substrate, an isolation region of the structure formed on a major surface of the Si substrate, a thin oxide grown on the major surface, and a germanium ion dopant implanted into the major surface of the Si substrate through the thin oxide and annealed, wherein the structure has a near constant threshold voltage V
t
over a range of device channel widths.
In another embodiment, the MOS devices are formed using local oxide isolation.
In yet another embodiment, the MOS devices are formed using shallow trench isolation techniques.
In another embodiment, the range of the device channel widths is between 1.0&mgr; and 10.0&mgr;, inclusively.
In yet another embodiment, the range of the device channel widths is less than or equal to 1.0&mgr; and greater than zero.
In another embodiment, the device channel widths are less than or equal to 0.5&mgr; and greater than zero.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.
REFERENCES:
patent: 4728619 (1988-03-01), Pfiester et al.
patent: 4885257 (1989-12-01), Matsushita
patent: 5314841 (1994-05-01), Brady et al.
patent: 5358879 (1994-10-01), Brady et al.
patent: 5360752 (1994-11-01), Brady et al.
patent: 5397909 (1995-03-01), Moslehi
patent: 5527724 (1996-06-01), Brady et al.
patent: 5891787 (1999-04-01), Gardner et al.
patent: 6121651 (2000-09-01), Furukawa et al.
patent: 6121660 (2000-09-01), Yamazaki et al.
patent: 6153476 (2000-11-01), Inaba et al.
patent: 6218219 (2001-04-01), Yamazaki et al.
patent: 6323082 (2001-11-01), Furukawa et al.
Brady Frederick T.
Maimon Jon
BAE Systems Information and Electronic Systems Integration Inc.
Jr. Carl Whitehead
Schillinger Laura M
Swidler Berlin Shereff & Friedman, LLP
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