Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-18
2002-08-06
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S687000
Reexamination Certificate
active
06429118
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills the pinholes or intra-cracks (micro-cracks) caused by poor gap filling of purely electrochemical deposition of copper plating, and therefore, prevents attack by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps.
(2) Description of Related Art
As an introduction and background to Prior Art, the conventional dual damascene process scheme is commonly used to fabricate copper interconnects, trench, and contact vias. Dual Damascene wiring interconnects (and/or studs) are formed by depositing one or two dielectric layers on a planar surface, patterning it using photolithography and dielectric reactive ion etch (RIE), then filling the recesses with conductive copper metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with inlaid metal. With the dual damascene process, two layers of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
The copper metal deposition in some Prior Art methods is performed by purely using an electrochemical deposition (ECD) of copper process, or various electroless copper plating methods, sometimes termed copper “auto-plating”. These copper plating processes has been shown to produce interconnect copper line damage, during chemical mechanical polishing (CMP) back of the excess copper metal. Surface voids and recesses have been observed, induced by poor gap filling of the electrochemical deposited (ECD) copper plating process. In addition, some pinholes and intra-crack (micro-cracks) have been found on the electrochemical deposited (ECD) copper surface. These “weak”, defective structures are easily attacked by the chemicals in the copper slurry, oxide slurry and post polishing cleaning steps.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 6,010,962 entitled “Copper Chemical Mechanical Polishing (CMP) Dishing” granted Jan. 4, 2000 to Liu et al. describes a process for copper chemical mechanical polishing (CMP), forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate, including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure. Then the photoresist is removed from the composite structure, and replaced with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal.
U.S. Pat. No. 5,877,084 entitled “Method for Fabricating High Aspect Ratio Low Resistivity Lines/Vias by Surface Reaction” granted Mar. 2, 1999 to Joshi et al. recites a method for fabricating high aspect ratio, low resistivity lines/vias, by surface reaction by forming a cap layer over a copper interconnect. The method describes the use of low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe.
U.S. Pat. 5,780,358 entitled “Method for Chemical Mechanical Polish (CMP) Planarizing of Copper Containing Conductor Layers” granted Jul. 14, 1998 to Zhou et al. shows Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers. The Chemical-Mechanical Polish (CMP) slurry composition is a non-aqueous coordinating solvent and halogen radical producing species.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming an integrated circuit in which copper line damage is eliminated for damascene processing, by depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills the pinholes or intra-cracks (micro-cracks) caused by poor gap filling of purely electrochemical deposition of copper plating, and therefore, prevents attack by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps.
The process embodiments of this invention start with the first process step, the forming by damascene and chemical mechanical polishing (CMP) the first level inlaid metal structures. The process sequence is as follows: an insulating layer is deposited. This first insulating layer, e.g., silicon oxide, is patterned and reactive ion etched (RIE) upon a semiconductor substrate. The next processing step in building of the damascene structure, is the deposition by sputtering (PVD, physical vapor deposition) and patterning of a thin metal barrier layer (trench liner), e.g. Ta,TaN, and a thin copper seed layer. Copper metal is deposited upon the seed layer in the openings in insulator by electrochemical copper deposition (ECD). The excess copper metal is polished off and planarized with surface by chemical mechanical polishing (CMP) forming the first level of conducting metal wiring.
Continuing with the summation of the process embodiments of this invention, is the second process step, the deposition of a copper metal protecting “buffer layer”. This layer is needed to prevent copper corrosion with silicon oxide layers. It is deposited over the first level inlaid metal structures and first insulator layer. This buffer layer is, e.g., silicon nitride. The third process step is the blanket deposition of an intermetal dielectric (IMD) layer upon the buffer layer. This intermetal dielectric (IMD) is, e.g., silicon oxide, silicon nitride, or FSG fluoro-silicate glass, or PSG phosphosilicate glass. The fourth step is to form a photoresist masking layer by a lithography process, defining damascene openings or trench/vias openings, over the first level of metal. Photoresist is coated and patterned upon the intermetal dielectric (IMD) layer. A reactive ion etch (RIE) is performed to etch the intermetal dielectric layer (IMD) layer, forming openings and stopping on the buffer layer. The fifth step is removal of the photoresist material and the metal protecting buffer layer in the exposed opening areas. The sixth and seventh steps are the deposition of both a metal diffusion barrier layer and a copper seed layer, over the patterned intermetal dielectric (IMD) layer and over the first level of conductor wiring, into the damascene openings.
The eighth step in this process, considered one of the key processing steps, is the electrochemical deposition (ECD) of copper metal, upon the seed layer. Another key embodiment of this invention now follows, in summary form. The ninth step of the process is considered to be the key process step, in achieving a smooth copper metal surface. This key step is the sputter deposition of a top copper layer upon the electrochemical deposited layer (ECD) copper layer, which is performed by physical vapor deposition (PVD), preferably by an ion metal pla
Chen Ying-Ho
Jang Syun-Ming
Shih Tsu
Twu Jih-Churng
Ackerman Stephen B.
Fahmy Wael
García Joannie Adelle
Saile George O.
Taiwan Semiconductor Manufacturing Company
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