Elimination of dendrite formation during metal/chalcogenide...

Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S674000, C438S796000

Reexamination Certificate

active

06825135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods of forming metal-chalcogenide glass structures and more particularly to a method of preventing formation of extraneous metal dendrite structures during fabrication of programmable conductor memory cells using metal-chalcogenide glass systems.
2. Description of the Related Art
The digital memory most commonly used in computers and computer system components is the dynamic random access memory (DRAM), wherein voltage stored in capacitors represents digital bits of information. Electric power must be supplied to the capacitors to maintain the information because, without frequent refresh cycles, the stored charge dissipates, and the information is lost. Memories that require constant power are known as volatile memories.
Non-volatile memories do not need frequent refresh cycles to preserve their stored information, so they consume less power than volatile memories. The information stays in the memory even when the power is turned off. There are many applications where non-volatile memories are preferred or required, such as in lap-top and palm-top computers, cell phones or control systems of automobiles. Non-volatile memories include magnetic random access memories (MRAMs), erasable programmable read only memories (EPROMs) and variations thereof.
Another type of non-volatile memory is the programmable conductor or programmable metallization memory cell, which is described by Kozicki et al. in U.S. Pat. No. 6,084,796 and is included by reference herein. The programmable conductor cell of Kozicki et al. (also referred to as a metal dendrite memory) comprises a glass ion conductor, such as a chalcogenide-metal ion glass, and a plurality of electrodes disposed at the surface of the fast ion conductor and spaced a distance apart from one another. The glass/ion element shall be referred to herein as a “glass electrolyte,” or, more generally, a “cell body.” When a voltage is applied across the anode and the cathode, a non-volatile metal dendrite grows from the cathode along the surface of the cell body towards the anode. The growth of the dendrite depends upon applied voltage and time; the higher the voltage, the faster the growth rate; and the more time, the longer the dendrite. The dendrite stops growing when the voltage is removed. The dendrite shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed.
The programmable conductor memory cell can serve as a “one” state when the conductive path has grown all the way from the cathode to the anode, thus providing a low resistance metallic conduction path. The programmable conductor memory cell is in a “zero” state when the conductive path is at least partially dissolved, and the metallic conduction path is broken and the resistance of the cell is several orders of magnitude higher. In other arrangements, varying extent of the conductive path can be used in forming variable capacitors or variable resistors.
The recent trends in memory arrays generally have been to first form a via, then fill it with a conventional memory storage element (e.g., a capacitor) and etch back. It is simple to isolate individual memory cells with this container structure. Following this trend, programmable memory cells have been also fabricated using this sort of container configuration, wherein the electrodes and body layers are deposited into a via etched into an insulating layer. Under normal operating conditions, conductive paths can grow between the electrodes, such as along the interface between the cell and the via wall. Typically, the memory cell is formed in an array having a conventional memory array circuit design. For example, in a conventional cross-point circuit design, memory elements are formed between upper and lower conductive lines at intersections. Typically, after forming the lower set of lines, a via is formed in an insulating layer and filled with the memory element, such as a glass electrolyte or glass fast ion diffusion (GFID) element.
Deposition of metal and chalcogenide glass is not simple. At normal deposition temperatures, metal atoms are highly mobile and can diffuse away from the glass or can form extraneous metal-rich structures, thus altering the component proportions in the deposited mixture and, thus, the performance of the programmable conductor memory cells.
Accordingly, a need exists for improved methods for depositing metal and chalcogenide glass to form integrated programmable conductor memory arrays.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method is provided for forming a programmable conductor memory cell. The method includes sputtering metal and chalcogenide glass onto a prepared substrate. The substrate is maintained at a temperature higher than room temperature during sputtering.
In accordance with another aspect of the present invention, a method is provided for depositing a metal/chalcogenide glass film with a desired metal to glass ratio onto a substrate. The method includes pre-heating the substrate to a desired temperature between about 40° C. and 130° C. Metal and chalcogenide glass are co-sputtering metal and chalcogenide glass onto the substrate after pre-heating. The substrate is held at the desired temperature during the co-sputtering.
In accordance with another aspect of the invention, a method is provided for co-sputtering a homogeneous metal/chalcogenide glass layer onto a irregular surface. The irregular surface is kept at an elevated temperature, above room temperature, before and during the co-sputtering.


REFERENCES:
patent: 3271591 (1966-09-01), Ovshinsky
patent: 3622319 (1971-11-01), Sharp
patent: 3743847 (1973-07-01), Boland
patent: 3961314 (1976-06-01), Klose et al.
patent: 3966317 (1976-06-01), Wacks et al.
patent: 3983542 (1976-09-01), Ovshinsky
patent: 3988720 (1976-10-01), Ovshinsky
patent: 4115872 (1978-09-01), Bluhm
patent: 4177474 (1979-12-01), Ovshinsky
patent: 4267261 (1981-05-01), Hallman et al.
patent: 4269935 (1981-05-01), Masters et al.
patent: 4312938 (1982-01-01), Drexler et al.
patent: 4316946 (1982-02-01), Masters et al.
patent: 4320191 (1982-03-01), Yoshikawa et al.
patent: 4405710 (1983-09-01), Balasubramanyam et al.
patent: 4419421 (1983-12-01), Wichelhaus et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4597162 (1986-07-01), Johnson et al.
patent: 4608296 (1986-08-01), Keem et al.
patent: 4637895 (1987-01-01), Ovshinsky et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4664939 (1987-05-01), Ovshinsky
patent: 4668968 (1987-05-01), Ovshinsky et al.
patent: 4670763 (1987-06-01), Ovshinsky et al.
patent: 4671618 (1987-06-01), Wu et al.
patent: 4673957 (1987-06-01), Ovshinsky et al.
patent: 4678679 (1987-07-01), Ovshinsky
patent: 4696758 (1987-09-01), Ovshinsky et al.
patent: 4698234 (1987-10-01), Ovshinsky et al.
patent: 4710899 (1987-12-01), Young et al.
patent: 4728406 (1988-03-01), Banerjee et al.
patent: 4737379 (1988-04-01), Hudgens et al.
patent: 4766471 (1988-08-01), Ovshinsky et al.
patent: 4769338 (1988-09-01), Ovshinsky et al.
patent: 4775425 (1988-10-01), Guha et al.
patent: 4788594 (1988-11-01), Ovshinsky et al.
patent: 4795657 (1989-01-01), Formigoni et al.
patent: 4800526 (1989-01-01), Lewis
patent: 4809044 (1989-02-01), Pryor et al.
patent: 4818717 (1989-04-01), Johnson et al.
patent: 4843443 (1989-06-01), Ovshinsky et al.
patent: 4845533 (1989-07-01), Pryor et al.
patent: 4847674 (1989-07-01), Sliwa et al.
patent: 4853785 (1989-08-01), Ovshinsky et al.
patent: 4891330 (1990-01-01), Guha et al.
patent: 5128099 (1992-07-01), Strand et al.
patent: 5159661 (1992-10-01), Ovshinsky et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5177567 (1993-01-01), Klersy et al.
patent: 5219788 (1993-06-01), Abernathey et al.
patent: 5238862 (1993-08-01), Blalock et al.
patent: 5272359 (1993-12-01), Nagasubramanian et al.
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5314772 (1994-05-01), Kozicki et al.
patent: 5315131 (1994-05-01), Kishimoto et al.
patent: 5350484 (

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Elimination of dendrite formation during metal/chalcogenide... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Elimination of dendrite formation during metal/chalcogenide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Elimination of dendrite formation during metal/chalcogenide... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3354471

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.