Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-02-20
2001-09-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S663000
Reexamination Certificate
active
06291337
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to semiconductor devices, and more particularly, to an improved process to eliminate cracks occurred during manufacturing a semiconductor wafer. Specifically, this invention relates to using an optimal temperature in a rapid thermal annealing (RTA or RTP) process or using an improved deposition process of a titanium nitride (TiN) layer before the RTA process to ensure cracks are not introduced into the TiN layer deposited on the semiconductor wafer.
BACKGROUND OF THE INVENTION
The electronic industry has long used an ion implantation technique to dope desired impurities into a semiconductor wafer. The ion implantation technique provides a much better control of a doping profile than other diffusion-type doping processes, such as, e.g., a chemical vapor deposition (CVD) process. However, during the ion implantation process, damages will be inevitably introduced into a crystal structure of the semiconductor wafer due to the bombardment of doping ions into the semiconductor wafer. The damages to the crystal structure of the semiconductor wafer will cause adverse effects on performance of chip products made from the semiconductor wafer. Annealing processes are thus needed to restore the crystal damages of the semiconductor wafer.
During the annealing process, annealing conditions, such as, e.g., temperature and time period of the annealing process, should be controlled precisely, otherwise, implanted dopants will diffuse within the semiconductor wafer and cause the desirable doping profile to be lost. Rapid thermal process (RTP), also called rapid thermal annealing (RTA), technology is therefore designed to provide an annealing process without losing the desired doping profile made by ion implantation.
The RTA technology offers fast surface heating that restores the damages of crystal without a substrate temperature of the wafer rising to a diffusion level for the implanted dopants. In addition, the RTA process can take place in seconds while a conventional tube thermal process used in annealing wafers may take from 15 to 30 minutes. The RTA technology is based on a principle of radiation heating where the semiconductor wafer to be annealed is placed in a chamber fitted with gas inlets and exhaust outlets. Inside the gas chamber, a heat source above, and possibly below, the wafer provides the rapid heating of RTA process. Tungsten halogen lamps or graphite heaters are examples, among others, used in the electronic industry for heat sources of the RTA technology. Because of its very short heating times with radiation heating, the body of the wafer never comes up to the dopant-diffusion temperature. Further, every time a wafer is heated and cooled in an annealing process, RTA or not, more crystal damages might be formed in the wafer. By minimizing a total annealing time and thermal budget, the RTA process allows more dense designs and fewer failures from crystal damages of the wafer. The RTA technology thus offers an ideal mean of annealing the crystal damages while maintaining the desirable doping profiled made by ion implantation.
Experiments performed by the inventors found that the conventional RTA process has introduced cracks into the semiconductor wafer, particularly to a titanium (Ti), titanium nitride (TiN) or a titanium nitride on titanium (TiN/Ti) barrier layer deposited over a boron phosphorus silicate glass (BPSG) layer on the semiconductor wafer.
Ti, TiN or TiN/Ti barrier layer acts as a glue for metal plugs or later metal layers, such as tungsten or aluminum plugs, used as contact plugs, via layers, in a semiconductor. Ti, TiN or TiN/Ti layers are also commonly used as a contact “barrier” for tungsten plugs or aluminum plugs of metal contacts for semiconductor devices to prevent spiking and alloying between an aluminum or tungsten interconnection and the silicon surface. Cracks created on the TiN or TiN/Ti barrier layer after the RTA process will thus destroy functionality, such as causing junction leakage problems, of the chip products and consequently reduce the yield rate of the semiconductor wafer. Experiments by the inventors show that cracks are particularly prevalent at the edge of the wafer and at deep contacts in the device.
An object to this invention is to provide an improved process for manufacturing semiconductor wafers thereby to eliminate all, or almost all, cracks causes to the wafer, and the chip products built on the wafer, during the RTA process.
SUMMARY OF THE INVENTION
A first embodiment of the present invention provides an improved process of a preferred temperature adopted during the RTA process to the semiconductor wafer.
According to principles of the present invention, in a first embodiment, the rapid thermal anneal temperature was kept below 600° C. The titanium layer and the TiN/Ti barrier was deposited without changing the titanium nitride formation conditions. Using the standard formation process conditions, rapid thermal anneal was carried out at a much lower temperature than previously used, less than 600° C. Preferably, the RTA temperature was in the range of 635° C. -590° C. The temperature may also be in the range of 570° C. -595° C.
Another embodiment of the present invention provides an improved deposition process for the TiN or TiN/Ti barrier layer so that it will not cause cracks during the RTA process.
According to another embodiment of the present invention, the process conditions for forming the titanium layer are modified to ensure that after the rapid thermal anneal, the tensile stress is lower than a selected amount. This is accomplished by using a lower deposition power than previously used, preferably in the range of 5.0-6.5 KW and, according to one embodiment, below 6.0 KW and in the range of 5.7-6.0 KW.
The features and advantages of the invention will be apparent from the following description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings.
Experiments performed by the inventors found that the conventional RTA process has introduced cracks into the semiconductor wafer, particularly to a titanium (Ti), titanium nitride (TiN) or a titanium nitride on titanium (TiN/Ti) barrier layer deposited over a boron phosphorus silicate glass (BPSG) layer on the semiconductor wafer.
Ti, TiN or TiN/Ti barrier layer acts as a glue for metal plugs or later metal layers, such as tungsten or aluminum plugs, used as contact plugs, via layers, in a semiconductor. TiN or TiN/Ti layer are also commonly used as a contact “barrier” for tungsten plugs or aluminum plugs of metal contacts for semiconductor devices to prevent spiking and alloying between an aluminum or tungsten interconnection and the silicon surface. Cracks created on the TiN or TiN/Ti barrier layer after the RTA process will thus destroy functionality, such as causing junction leakage problems, of the chip products and consequently reduce the yield rate of the semiconductor wafer. Experiments by the inventors show that cracks are particularly prevalent at the edge of the wafer and at deep contacts in the device. One advantage of the present invention is that cracks are not created in the Ti, TiN or TiN/Ti layers. Therefore, possible cracking of underlying dielectric layers such as a ESPG layer is also prevented. This creates increased reliability in existing die and significantly increases yields of good die from the entire chip.
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Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
Lee Calvin
Smith Matthew
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