Eliminating unnecessary data pre-fetches in a multiprocessor...

Details Eliminating unnecessary data pre-fetches in a multiprocessor... Eliminating unnecessary data pre-fetches in a multiprocessor...

2005-03-29

2005-03-29

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S213000, C712S207000, C712S237000

Reexamination Certificate

active

06874067

ABSTRACT:
A multiprocessor computer system employs a number of levels of cache memories with each processor. A cache controller for a lower level cache memory receives a memory block pre-fetch request which requests a particular memory block. The cache controller determines a likelihood that the particular memory block will be invalidated prior to use of the memory block by a processor which issued the pre-fetch request. Based on that determination, the cache controller determines whether to honor the pre-fetch request.

REFERENCES:
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5721865 (1998-02-01), Shintani et al.
patent: 5881303 (1999-03-01), Hagersten et al.
patent: 6134634 (2000-10-01), Marshall et al.

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