Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-06-13
2009-08-04
Patel, Nitin C (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S503000
Reexamination Certificate
active
07571340
ABSTRACT:
Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.
REFERENCES:
patent: 4694472 (1987-09-01), Torok et al.
patent: 6038254 (2000-03-01), Ferraiolo et al.
patent: 6285864 (2001-09-01), Ruemmer et al.
patent: 6611475 (2003-08-01), Lin
patent: 6759882 (2004-07-01), Lin
patent: 6978403 (2005-12-01), Takei et al.
patent: 7072432 (2006-07-01), Belcea
patent: 7168027 (2007-01-01), Lee et al.
patent: 7400671 (2008-07-01), Hampel et al.
patent: 2003/0217301 (2003-11-01), Levy et al.
patent: 2004/0223566 (2004-11-01), Yamashita
patent: 2005/0089127 (2005-04-01), Nagaraja
patent: 2006/0184697 (2006-08-01), Virdi et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Patel Nitin C
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