Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-01
2001-04-03
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S384000, C257S340000, C257S336000, C257S344000
Reexamination Certificate
active
06211556
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more specifically, to MOSFET (metal oxide semiconductor field effect transistor) devices having self-aligned silicide and buried contact connection free of buried contact trench.
BACKGROUND OF THE INVENTION
From the first invention of integrated circuits in 1960, the number of devices on a chip has grown at an explosively increasing rate. The technologies of the semiconductor industry have been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has stepped into the ULSI (ultra large scale integration) level or at an even higher level. The capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices, or even billions of devices. The integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed simultaneously to accommodate the continuously raising requirements.
The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within a smaller size without damaging the characteristics and the operations. The demands on high packing density and low heat generation devices with good reliability and long operation life must be maintained without any degradation in their functions.
All the challenges and demands in fabrication arc expected to be solved with the four key aspects of the semiconductor manufacturing, including the lithography, the film formation, the etching, and the diffusion processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. In addition to chip area and functional considerations, all the devices with smaller size must be achieved with simplified and reliable manufacturing steps to raise the yield and reduce the cost of the products.
In the application of memory devices, the SRAM device plays a vital role as a semiconductor storage cell in which the stored data can be latched without degradation. Typically, a SRAM cell is composed of bistable transistor flip-flops which can be implemented in various configurations. MOS (metal oxide semiconductor) field effect transistors or bipolar transistors are used in the bistable transistor flip-flops. The SRAM cell utilizes more transistors than a typical DRAM (dynamic random memory) cell which has only one transistor and one capacitor for each unit cell. With more transistors employed in forming memory arrays, the packing density of MOSFET devices in the SRAM array is of great consideration. The packing density must be raised greatly to include more memory cells in a single chip.
The buried contact technology, which utilizes doped poly-crystalline silicon or titanium nitride (TiN) layers for local interconnect, has been widely applied to the modern integrated circuits, such as SRAM and BiCMOS devices. In U.S. Pat, No. 4,701,423 to N. J. Szluk, a totally self-aligned CMOS process is disclosed. It is disclosed that the buried contacts or self-aligned buried contacts is one of the beneficial structures in improving device performance and device density. However, it is difficult to implement the buried contacts with some other beneficial structures like LDD (lightly doped drain), gate/conductor doping, and self-aligned contacts. The process complexity is increased and the device yield is hard to maintain. A CMOS process which incorporates lightly doped drain-source structures, sidewall oxide structures and self-aligned contacts is disclosed in the invention.
M. H. El-Downy et al. disclose the use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers in U.S. Pat. No. 5,082,796. It is addressed that the number of metal layers formed on a given portion of a wafer is limited. Therefore, the use of a polysilicon layer for local interconnect allows the metal layer that was formerly used for local interconnect to be employed as an additional global connection layer. The use of a polysilicon layer to form device contacts also results in the improvement in transistor performance through reduction in device parasitic areas.
The buried contacts provide the electrical interconnection among gate electrodes, drain regions of the cross-coupled MOS transistors and source/drain regions of the transmission-gate transistors. However, the typical buried contacts have a major problem in the formation of the buried contact trench which interrupts the transistor current flow path causing device failure.
In U.S. Pat. No. 5,580,806 to T. T. Chang et al., a method of fabricating a buried contact structure for SRAM is disclosed. The buried contacts are used in a MOS SRAM cell, which employs two loads and two cross-coupled MOS transistors to connect each gate electrode to the drain region of the opposing cross-coupled MOS transistors. The trench formation problem in conventional application of the buried contact technology is also illustrated in the invention. The resistance is increased under the reduction of the impurity dosage.
Y. H. Wu et al disclose a trench free process for SRAM in U.S. Pat. No. 5,705,437. The formation of undoped region or trench is introduced to increase the electrical resistivity or leakage problem. However, the conventional processes in solving the trench formation problem generally incorporate complicate processing steps. The efforts needed in fabrication is thus increased as well as the cost. What is needed is a method to form trench-free buried contacts with simplified process.
SUMMARY OF THE INVENTION
A method for eliminating buried contact trench in MOSFET (metal oxide semiconductor field effect transistor) devices with self-aligned silicide is disclosed in the present invention. A simpler process than conventional buried contact process is provided with improved device performance and characteristics. MOSFET (metal oxide semiconductor field effect transistor) devices having self-aligned silicide are also disclosed and provided with buried contact connection free of buried contact trench.
A MOSFET device with buried contact structure on a semiconductor substrate has following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region abuts the lightly doped source/drain region and is located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection. Specifically, the shielding block includes dielectric sidewalls and silicon sidewalls and the shielding block is formed right next to the edge of the silicon connection.
In addition to the aforementioned elements, the MOSFET device can further include metal silicide on the doped source/drain region, the silicon connection, and the gate electrode, in order to provide improved contacts. As to the structure of connections, the MOSFET device further includes a dielectric layer over the silicon connection, the substrate, the gate sidewall structure, and the gate electrode and an interconnection structure in the dielectric layer having electrical contacts with the silicon connection and the gate electrode, preferably through the metal silicide.
REFERENCES:
patent: 5315150 (1994-05-01), Furuhata
patent: 5317197 (1994-05-01), Roberts
patent: 5596215 (1997-01-01), Huang
patent: 5926706 (1999-07-01), Liaw et al.
patent: 6107642 (2000-08-01), Sundaresan
patent: 5-206066 (0000-01-01), None
Fenty Jesse A.
Lee Eddie C.
Texas Instruments - Acer Incorporated
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