Elevated source/drain MOSFET with solid phase diffused source/dr

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

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257221, 257410, 257412, 257650, 257644, H01L 2976

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active

059775610

ABSTRACT:
The MOSFET has a stacked gate structure which has a first silicon layer, a second silicon layer, and a spacer structure. The first silicon layer is formed over the semiconductor substrate. The second silicon layer contains second type dopants and is formed on the first silicon layer. The spacer structure containing first type dopants is formed on the sidewall of the first silicon layer and the second silicon layer. A gate insulator layer is formed between the first silicon layer and the semiconductor substrate. The second silicon layer is also formed on the semiconductor substrate at a region uncovered by the stacked gate structure. A junction region is formed in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. An extended junction is formed in the semiconductor substrate under the spacer structure.

REFERENCES:
patent: 4435897 (1984-03-01), Kuroda et al.
patent: 5221852 (1993-06-01), Nagai et al.
patent: 5793059 (1998-08-01), Park
patent: 5796151 (1998-08-01), Hsu et al.
Kiyoshi Takeuchi et al., High performance sub-tenth micron CMOS using advanced boron doping and WSI.sub.2 dual gate process, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 9 and 10.
Shye Lin Wu et al., Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (.ltoreq.7nm) by Using a Stacked-Amorphous-Silicon(SAS) Film, 1993 IEEE, pp. 329-332.
T.P. Ong et al., CVD SiN.sub.x Anti-reflective Coating for Sub-0.5.mu.m Lithography, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 73 and 74.
Tan Fu Lei et al., Low-Temperature Growth of Silicon-Boron Layer as Solid Diffusion Source for Polysilicon Contacted p.sup.+ -n Shallow Junction, 1995 IEEE, pp. 2104-2110.

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