Elevated CMOS

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257334, 257369, 257372, 257377, H01L 2702, H01L 2978, H01L 2701, H01L 2906

Patent

active

052930530

ABSTRACT:
A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.

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patent: 4566914 (1986-01-01), Hall
patent: 4660062 (1987-04-01), Nishizawa et al.
patent: 4670768 (1987-06-01), Sunami et al.
patent: 4713678 (1987-12-01), Womack et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 4984030 (1991-01-01), Sunami et al.
patent: 5072276 (1991-12-01), Malhi et al.

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