Electrostatic-protection dummy transistor structure

Details Electrostatic-protection dummy transistor structure Electrostatic-protection dummy transistor structure

2007-03-27

2007-03-27

Le, Thao X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000

Reexamination Certificate

active

10810668

ABSTRACT:
A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistor11are connected respectively to an output electrode and to ground, is an NMOS protection transistor10of which the drain and source are connected respectively to the drain and source of the NMOS output transistor11and of which the gate is directly connected to a second-conductivity-type layer, a P-well22, under the gate electrode of the NMOS output transistor11. By this means, an electrostatic surge does not concentrate in the NMOS output transistor11.

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