Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-17
2003-11-11
Ngo, Ngan V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S360000, C257S361000, C257S363000, C257S364000
Reexamination Certificate
active
06646309
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor MOS technology, such as CMOS, and more particularly to preventing electrostatic discharge (ESD) event-related problems within semiconductor devices using such MOS technology.
BACKGROUND OF THE INVENTION
Salicide is widely used in deep sub-micron CMOS technology to lower the sheet resistance of the polysilicon resistors and the MOS junction sources and drains of CMOS devices. Without employing selective salicide blocking, however, the electrostatic discharge (ESD) performance of full salicide CMOS semiconductor devices is jeopardized. Selective salicide blocking includes utilizing a salicide blocking mask to remove salicide from the source and drain of the NMOS channel of such a device. Without using such salicide blocking, however, the resulting CMOS device has non-uniform turn-on behavior between the fingers of the device, causing thermal runaway at the MOS channel of the device.
It is known that adding a ballast resistor between the bonding pad and the drain of the NMOS transistor can increase the uniformity of the turn-on voltage (i.e., breakdown voltage) for the parasitic, npn-bipolar junction transistor (BJT) underneath the NMOS channel. Removing the salicide from the drain of the NMOS transistor creates such a ballast resistor, increasing the uniformity of the turn-on voltages of the parasitic npn-BJT's between the fingers. Blocking the salicide on the drain area can increase the effective collector area of the parasitic npn-BJT underneath the NMOS channel. Employing a salicide blocking mask to remove the salicide from the drain of the NMOS channel is thus helpful in bettering ESD performance.
The prior art teaches that this can be accomplished by using a multi-finger turn-on (MFT) technique. This technique teaches inserting salicide polysilicon resistors between the sources of the NMOS channels and ground, to ensure that all fingers are triggered in the case of an ESD event. However, insertion of such resistors is disadvantageous. The sheet resistance of the salicide polysilicon resistor, for instance, may change after the occurrence of an ESD event, causing a corresponding change in the devices' current-voltage (I-V) curve. For this reason, as well as other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to employing an electrostatic discharge (ESD) trigger to trigger the MOS transistors (i.e., the ESD fingers) within a CMOS device to provide substantially more uniform turn-on voltages for the MOS transistors, resulting in better ESD device performance without employing selective salicide blocking. A semiconductor device of an embodiment of the invention has an ESD trigger and a number of ESD fingers. The turn on voltage of the ESD trigger is less than the turn on voltage of the ESD fingers, such that the ESD fingers turn on substantially uniformly after the ESD trigger turns on during an ESD event. The semiconductor device is substantially fabricated without employing salicide blocking.
Embodiments of the invention provide for advantages not found within the prior art. ESD protection is achieved by the invention without utilizing salicide blocking in semiconductor devices having salicide. Thus, the disadvantages associated with utilizing salicide blocking as in the prior art are avoided. That is, the sheet resistance of the salicide polysilicon resistor of the device preferably does not deviate after the occurrence of an ESD event, such that the device's current-voltage (I-V) curve also does not deviate after the occurrence of the ESD event. Still other aspects, embodiments, and advantages of the invention will become apparent by reading the detailed description that follows, and by referring to the accompanying figures.
REFERENCES:
patent: 6078083 (2000-06-01), Amerasekera et al.
patent: 6501632 (2002-12-01), Avery et al.
patent: 2002/0149059 (2002-10-01), Ker et al.
patent: 2002/0154462 (2002-10-01), Ker et al.
patent: 2002/0154463 (2002-10-01), Mergens et al.
Ngo Ngan V.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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