Electrostatic discharge protective device having a reduced curre

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361111, 361 91, 257355, H02H 904

Patent

active

055109470

ABSTRACT:
In an anti-ESD protective structure, especially designed for pins destined to reach below ground and/or above supply voltages, includes a pair of Zener diodes or lateral NPN structures with a resistive connection between base and emitter, connected in opposition among each other between the pin to be protected and a grounded substrate of the integrated circuit. An amplifying effect on the leakage current which is drawn/injected through the pin by the protective structure caused by the triggering of an intrinsic parasitic transistor is effectively eliminated by connecting a biasing element, such as a forward biased junction, between the node of interconnection between the two Zener orlateral NPN structures and a node of the integrated circuit biased with a voltage sufficiently high as to ensure, under any condition, a reverse biasing of the base-emitter junction of the parasitic transistor.

REFERENCES:
patent: 4158863 (1979-06-01), Naylor
patent: 4302792 (1981-11-01), Harwood
patent: 4922371 (1990-05-01), Gray et al.

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