Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-06
2001-10-30
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S361000, C257S362000, C257S363000
Reexamination Certificate
active
06310380
ABSTRACT:
TECHNICAL FIELD
The present invention relates to electrostatic discharge protection transistor structures and more particularly to electrostatic discharge protection transistor structures using shallow trench isolation.
BACKGROUND OF THE INVENTION
Electrostatic discharges (ESDs) are caused by high-voltage spikes of static charges. Damage from electrostatic discharge is a significant failure mechanism in modern integrated circuits, particularly as integrated circuit physical dimensions continue to shrink to the submicron range.
A major source of ESD is from the human body. A charge of about 0.6 muC can be induced on a body capacitance of 150 pF leading to electrostatic potentials of 4 kV or greater. Any contact by a charged human body with a grounded object, such as the pin of an integrated circuit, can result in a discharge in about 100 nseconds with peak currents of several amperes to the integrated circuit. This is described as the “human body model”, or HBM, ESD source.
A second source of ESD is from metallic objects. The metallic object ESD source is characterized by a greater capacitance and a lower internal resistance with ESD transients having significantly higher rise times than the HBM ESD source. This is described as the “machine model”, or MM, ESD source.
A third ESD source is from the integrated circuit itself. The integrated circuit becomes charged and discharges to ground. Thus, the ESD discharge current flows in the opposite direction in the integrated circuit than that of the HBM ESD source and the MM ESD source. This is described as the “charged device model”, or CDM, ESD source.
Electrically, an ESD occurs upon contact of one or more of the terminals of an integrated circuit with a body or material that is statically charged to a high voltage. This level of static charge is readily generated by the triboelectric effect, and other mechanisms acting upon humans, equipment, or the circuits themselves. Upon contact, the integrated circuit discharges through its active devices and DC current paths. If the amount of charge is excessive however, the discharge current density can permanently damage the integrated circuit so that it is no longer functional or so that it is more prone to later-life failure. ESD damage thus is a cause of yield loss in manufacturing and also poor reliability in use.
Currently, it is a common practice in the art to implement ESD protection devices connected to the external terminals of the circuit. ESD protection devices are designed to provide a current path of sufficient capacity to safely discharge the current applied by a charged body in an ESD, but not to inhibit functionality of the integrated circuit in normal operation. The addition of ESD protection devices necessarily adds parasitic effects that degrade circuit performance. In some cases such as in series resistors, the ESD protection devices directly add delay to the electrical performance.
Accordingly, it is a desirable goal for ESD protection devices to provide a high-capacity current path, which is readily turned-on during an ESD, but which can never turn-on during normal operation and which presents minimal effect on circuit performance.
In the past, n-type metal oxide semiconductor (NMOS) transistors have been widely used as ESD protection devices in semiconductor integrated circuit devices. However, with these transistors, it is well know to those skilled in the art that salicidation (self-aligned siliciding) of the drain and the source junctions reduces ESD performance significantly. From the ESD viewpoint, the primary effect of the salicidation is to bring a transistor drain or a source contact closer to its diffusion edge near their respective gate edge. The consequence is that under high current conditions, the ballasting resistance between the drain or the source contact and their respective gate edge is reduced and the current path\ cause “hot spot” formation, usually at the gate edge. Once a hot spot is formed, there is very little resistance to prevent current localization through the hot spot and so most of the current flows through the silicide to the gate edge. This leads to higher power dissipation and damage in this region. Also, the high power dissipation through the drain or source silicide can cause damage at the drain or source contact when the eutectic temperature is exceeded.
The most conventional solution to the salicidation problem is to add an additional photolithographic process step, called a “salicide block”. Most salicidation fabrication technology processes have a salicide block option which blocks the formation of silicide in areas close to a transistor's gate edge. Without the gate edge silicide, an ESD implantation is required make the drain junction deeper as well as to overdope the lightly doped region of the LDD for better ESD performance. Since the ESD implantation is undesirable in the circuitry being protected, an ESD implant block would be required over the non-ESD circuitry. Thus, this approach adds to process complexity because it requires at least two additional photolithographic process steps; i.e., the silicide block and the ESD implant block.
Another way to provide ESD protection is to use a grounded gate thin oxide n-type MOS (GGNMOS) transistor. In the GGNMOS transistor, the voltage necessary to turn the transistor on (the turn-on voltage) is reached before the occurrence of an avalanche breakdown due to voltage across the gate oxide of the transistor. Unfortunately, as these transistors continue to shrink in size down to the deep-quarter-micron geometry level, the gate oxide becomes so thin that the gate oxide breakdown voltage approaches the turn-on voltage. Thus, the protection window tends to go to zero and at a small enough geometry will provide no protection at all.
Therefore, it is critical that a new form of ESD protection circuit be developed for smaller integrated circuit geometries that is compatible with saliciding technology without adding process complexity or cost.
DISCLOSURE OF THE INVENTION
The present invention provides a transistor structure for ESD protection in an integrated circuit device. A trench controls salicide deposition to prevent hot spot formation and allows control of the turn-on voltage. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusion regions on either side of the gate. A drain trench is located to separate the salicide between a drain contact and the gate edge, and by controlling the size and location of the drain trench, the turn-on voltages can be controlled; i.e., the turn-on voltage due to drain diffusion region to substrate avalanche breakdown and the turn-on voltage due to drain well to source well punch-through. Thus, very low turn-on voltages may be achieved for ESD protection.
The present invention provides a transistor structure for ESD protection in an integrated circuit device. A trench is used to block the salicide formation and to control the turn-on voltage by n-well punch-through. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusions on either side of the gate. A source trench is located between a source contact and the gate edge to reduce current localization and prevent hot spot formation during a CDM ESD, and to reduce positive ESD pulses turn-on voltages from drain to source during a HMB ESD.
The present invention further provides a transistor structure for an ESD protection circuit in an integrated circuit device that has uniform current flow through the structure and is not subject to hot spot formation.
The present invention further provides a transistor structure for an ESD protection circuit in an integrated circuit device that is compatible with self-aligned silicide fabrication technology without adding any process complexity or cost.
The present invention further provides a transistor structure for an ESD protection circuit in an integrated circuit de
Cai Jun
Lo Keng Foo
Chartered Semiconductor Manufacturing Inc.
Flynn Nathan
Ishimaru Mikio
Sefer Ahmed N.
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