Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-28
2003-06-24
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S367000
Reexamination Certificate
active
06583476
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a structure and a method for protecting an integrated circuit against internal circuit damages caused by electrostatic discharge (ESD) and, in particular, to a method for providing ESD protection at the power supply pins using channel stop field plates.
DESCRIPTION OF THE RELATED ART
Electrostatic discharge (ESD) is a well-known concern when designing an integrated circuit (IC). ESD events can occur at the input/output pads of an IC or the power supply pins. The ESD spikes can reach up to several thousand volts and can destroy circuitry within an IC, such as field effect transistors (FETs). When an ESD event occurs at an input/output pad of an IC, the resulting damages, such as leakage or shorts of the input/output pins, are usually localized at the input/output pad or nearby circuitry. However, when an ESD event occurs at the power supply pins, damages to the internal circuitry of the IC can result.
FIG. 1
is a cross-sectional view of a conventional semiconductor device fabricated using a BiCMOS process for illustrating the effect of an ESD event at a power supply pin. Referring to
FIG. 1
, semiconductor device
10
is fabricated on a P-type substrate
12
. In a BiCMOS process using a P-type substrate, junction isolation is typically used to isolate the passive and active devices. For instance, p-type devices are placed in N-wells while n-type devices can be placed directly in the substrate or in P-wells if a twin-well process is used. N-wells in a P-type substrate are connected to the highest voltage supply of the integrated circuit, such as the Vdd voltage, to ensure that the wells are reversed biased with respect to the substrate.
In
FIG. 1
, semiconductor device
10
includes a p-type diffusion resistor
15
and is isolated from P-type substrate
12
by an N-well
14
. N-well
14
includes n+ diffusion regions
20
for electrically connecting N-well
14
to the most positive power supply of the semiconductor device which in the present illustration is the Vdd voltage. Diffusion resistor
15
is formed by a P-well
16
formed inside N-well
14
. Two p+ diffusion regions
18
provide the resistor terminals R
1
and R
1
′. Note that the cross-sectional view of semiconductor
10
is simplified for ease of description. One of ordinary skill in the art would appreciate that semiconductor device
10
may include other structures and layers to facilitate the electrical connections of the different diffusion regions in the device.
When an ESD event occurs on the Vdd pin of semiconductor device
10
, the ESD energy can cause junction damage at the n+ diffusion regions
20
, resulting in shorting between the n+ regions and the p+ regions of diffusion resistor
15
and ultimately destroying the resistor. Thus, an ESD event at the power supply pin can cause damages to internal circuitry of an IC.
It is known to include a large resistance in series between the power supply terminal and the N-well contacts to provide ESD protection of the N-wells. Such resistance is typically added by connecting a resistor to the power supply pad. The inclusion of such resistors consumes silicon real estate and ultimately increases the size of the integrated circuit.
It is desirable to provide ESD protection of the power supply pin in an integrated circuit while minimizing the layout area of the integrated circuit.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a semiconductor structure formed in a semiconductor substrate of a first conductivity type for protecting against electrostatic discharge includes a first well of a second conductivity type formed in the substrate and having a first dopant concentration, a first region formed in the first well where the first region is of the second conductivity type and has a second dopant concentration greater than the first dopant concentration, an oxide region formed in and above a top surface of the semiconductor substrate where the oxide region encircles an active region in which one or more circuit elements are formed, and a field plate formed on the oxide region and encircling the active region. The field plate has a first end and a second end, where the first end of the field plate is coupled to a first power supply terminal and the second end of the field plate is coupled to the first region.
In operation, the field plate is used to introduced a resistance between the power supply pin and connections to N-wells or the N-substrate, thereby providing protection to the wells or substrate against damages caused by an ESD event.
REFERENCES:
patent: 5903420 (1999-05-01), Ham
patent: 6144070 (2000-11-01), Devore et al.
patent: 2210197 (1989-06-01), None
Mallikarjunaswamy Shekar
Miller Douglas
Cook Carmen C.
Micrel Inc.
Patent Law Group LLP
Wilson Allan R.
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