Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-11
2003-06-10
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S356000, C257S357000, C438S133000, C438S140000, C438S527000
Reexamination Certificate
active
06576960
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to protection circuits for semiconductor devices and, more specifically, to an electrostatic discharge protection circuit having a graded junction for shunting current through a substrate, and a method for forming the protection circuit.
BACKGROUND OF THE INVENTION
An electrostatic discharge (ESD) is a high-stress condition that can destroy integrated circuits. Particularly at risk are Metal Oxide Semiconductor (MOS) circuits, due to the presence of a thin gate oxide. As integrated circuits have decreased in size, gate oxide thickness has also decreased, currently having thicknesses of roughly 100 angstroms. At this thickness, a voltage of only around 10 volts can destroy the oxide during a discharge event. MOS integrated circuits are especially sensitive to damage from an ESD.
An ESD event begins when two areas of the chip are at different potentials and are separated by an insulator. If the potential difference between these two areas becomes large enough, current flows through the insulator in an attempt to equilibrate the charge. This current may destroy the insulative properties of the insulator, rendering the chip inoperative.
ESDs are carried to the integrated circuit through external terminals or pins. The pins of the integrated circuit are normally coupled to the integrated circuit through respective bonding pads formed on the integrated circuit. Therefore, for ESD protection to be effective against externally applied ESDs, the ESD protection should be near the bonding pad. ESD protection circuits are useful not only during operation of the chip, but also when a chip is not secured within an electronic device, such as during installation, or other times when the chip is being handled.
Some areas of the integrated circuit coupled to the pins are more susceptible to damage than others. For example, a ground plane and a Vcc plane within a chip are relatively large and spread out over the majority of the chip. These planes have a large capacitance with respect to the substrate. Consequently, these planes can sink a large amount of current without damage to an insulative layer separating the planes from the substrate. Conversely, each separate DQ circuit, which is coupled to part of the circuit yielding only 1 bit of data, is particularly susceptible to an ESD because the brunt of the ESD is borne by the relatively small output buffer circuitry. Thus, an ESD carried through a pin coupled to one of the DQ circuits is potentially more dangerous to the integrated circuit than an ESD carried through a pin coupled to the ground or Vcc plane.
Some prior art circuits for minimizing or eliminating damage due to an ESD include resistors, serially or parallel connected diodes, silicon controlled rectifiers, or other devices integrated into the substrate of the integrated circuit for limiting the currents of the ESD. One such prior art ESD protection circuit
2
is shown in FIG.
1
. An NMOS transistor
4
is formed in a substrate
6
that is biased at a ground potential. The transistor
4
includes a drain
8
connected to an input lead
10
that is coupled through a bonding pad (not shown) to an external terminal or pin of a chip. The bonding pad is also coupled to another circuit on the chip (not shown) that is being protected by the protection circuit
2
, such as an output buffer. The transistor
4
also includes a source
12
and a gate
14
, both of which are tied to a ground voltage. The gate
14
is separated from the substrate
6
by a gate oxide
18
. A pair of field oxide regions
16
separate the protection circuit
2
from the rest of an integrated circuit. If an electrostatic potential difference between the input lead
10
and the substrate
6
becomes greater than a trigger voltage, a discharge between these two areas occurs. Since the chip that includes this protection circuit
2
may be loose, uninstalled, or have no power applied to it, the ground voltage may be at a voltage much higher or much lower than a typical ground voltage of 0 volts. Similarly, the input lead
10
could likewise be at almost any potential, above or below the level of the substrate. The important consideration is not the absolute potential of the input lead
10
and the substrate
6
, but rather their potential difference.
Two kinds of ESDs exist, positive and negative. In a negative ESD, the input lead
10
is coupled to a negative voltage of sufficient magnitude with respect to the substrate
6
to trigger an ESD with current flowing from the chip through the input lead
10
. Negative ESDs typically do less damage to the chip than positive ESDs. One reason negative ESDs do less damage than positive ESDs is that, during a negative ESD, the MOS transistor
4
turns on because the input lead
10
is more negative with respect to the gate
14
than the threshold voltage of the MOS transistor. Thus, current flows from the grounded source
12
, which is acting as a drain, across a channel formed at the top surface of the substrate
6
and into the drain
8
, which is acting as a source. Additionally, if the voltage applied to the input lead
10
is lower with respect to the substrate
6
than the turn on voltage of the junction between the substrate and the drain
8
, charge will additionally flow directly from the substrate and into the drain. Thus, there are multiple paths available to carry the current flowing from the ground plane to the output terminal during a negative ESD.
During a positive ESD, the MOS transistor
4
does not operate as an MOS transistor, but rather becomes a current conduction mechanism operating like a bipolar NPN transistor. This bipolar transistor is made of the N-type drain
8
, the P-type substrate
6
and the N-type source
12
, corresponding respectively to a collector, base, and emitter. During a positive ESD event, the voltage applied to the drain
8
increases relative to the substrate
6
, thus increasing the reverse bias along the drain
8
—substrate
6
junction and increasing a space charge depletion region between these areas. The drain voltage continues to increase until the electric field across the depletion region becomes high enough to induce avalanche breakdown with the generation of electron-hole pairs. Generated electrons are swept through the depletion region and into the drain
8
towards the input lead
10
, while generated holes drift through the substrate towards the ground contact. As current flows into the substrate
6
, which is resistive, its voltage increases with respect to the source
12
. Eventually the substrate potential becomes high enough to forward bias the substrate
6
—source
12
junction, causing electrons to be emitted into the substrate from the source
12
. Eventually, the NPN transistor is fully turned on with current flowing from the collector to the emitter.
As more current flows through the drain
8
, it eventually causes localized heating along portions of the junction of the drain
8
and the substrate
6
, especially near the field oxide regions
16
. This localized heating can lead to physical breakdown, and eventual circuit inoperability. The curved nature of the drain
8
—substrate
6
boundary causes a large electric field to exist at a curved area
20
of the drain. Due to this increased electric field, The current density is higher through the curved area
20
of the drain
8
than other parts of the drain during an ESD event. This effect is called charge crowding. Because of charge crowding, the drain
8
and the substrate
6
break down at the curved area
20
before other areas of the junction between them. This curved area
20
causes the chip to be susceptible to damage at a lower level of ESD than it otherwise would if the curved area
20
was not present. Because positive ESDs do more damage to integrated circuits than negative ESDs, protection circuits are designed to withstand the more dangerous positive ESDs. Thus, the invention will only be described as it relates to positive ESDs.
An additional problem with the prior art circuit
2
of
FIG.
Casper Stephen
Duesman Kevin
Ma Manny K.
Porter Stephen R.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Vockrodt Jeff
Zarabian Amir
LandOfFree
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