Electrostatic discharge protection device

Details Electrostatic discharge protection device Electrostatic discharge protection device

2003-05-22

2004-03-30

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S360000

Reexamination Certificate

active

06713818

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an on-chip electrostatic discharge protection device, which is provided on a chip and protects an internal circuit against electrostatic discharge.
2. Description of the Related Art
The recent complex and high density design of semiconductor devices is bringing about such a problem that semiconductor devices are damaged by electrostatic discharge (ESD) during an assembling process or the like in the fabrication process. As one measure against the problem, an on-chip electrostatic discharge protection device (hereinafter also called “ESD protection device”), which protects elements in an internal circuit by efficiently discharging an electrostatic discharge current in a safe path, is provided in the chip of a semiconductor device.
Conventionally, a protection device comprised of a protection resistor and a diode has been used as an ESD protection device for a circuit device, such as CMOSLSI. However, the use of ESD protection devices that utilize the snap-back phenomenon of an MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which has a lower resistance and a better voltage clamping performance, is gradually becoming popular.
In an ESD protection device comprised of an MOSFET, as a large current is input to the drain of the MOSFET, the PN junction on the drain side causes avalanche breakdown, so that the current flows toward the substrate and is absorbed by, for example, the ground contact, such as a latch-up preventing P
+
guard ring. A potential difference occurs along the current path in accordance with the product of the resistance of the path and the current value, thereby increasing the local potential of the substrate. As a result, the potential of the PN junction on the source side increases to cause conduction, thereby further increasing the current that flows toward the substrate. Positive feedback occurs on the current that flows toward the substrate, so that the PN junction on the source side is forward-biased spontaneously, i.e., within a time of less than one nano second and comes to the operational state of a parasitic bipolar. This forms a low-resistance current path.
In such a case of using an MOSFET as an ESD protection device, the entire width of the MOSFET should be set to the order of about several hundred micrometers to ensure a sufficiently low resistance of several ohms in order to demonstrate the adequate protecting performance. Normally, small transistors whose widths are of about 10 to 100 &mgr;m (which are called “fingers”) are laid out in parallel are used.
Such a MOSFET type ESD protection device however has the following problems. Because the current is apt to concentrate on the drain-side end portion of the MOSFET type ESD protection device, the drain-side end portion of the gate electrode generates heat, so that the MOSFET type ESD protection device is likely to break down. Further, as the timings at which the individual fingers snap back to have a low resistance differ from one another, the current concentrates on the that finger which has snapped back faster so that the finger is likely to break down. Those shortcomings lower the protecting performance of the MOSFET type ESD protection device. Therefore, it is important for the MOSFET type ESD protection device to take some measures to prevent the excess current from flowing to the end portion of the gate electrode and to allow the current to evenly flow in all the fingers in the widthwise direction of the transistor.
An MOSFET has another problem such that it is technically difficult to lower its high holding voltage. To make the fabrication cost for semiconductor devices low, it is necessary to increase (the protecting performance/layout area) ratio of an ESD protection device. However, reducing the layout area increases the resistance of the MOSFET, thereby lowering the protecting performance. There is a limit to reduction in the resistance of an MOSFET per unit area, thereby limiting an improvement on (the protecting performance/layout area) ratio.
In this respect, attention is being paid to an SCR (silicon controlled rectifier) type ESD protection device. The SCR type ESD protection device is described in, for example, U.S. Pat. No. 5,502,317 and IEEE Electron Device Letters, Volume 12, Issue 1, January 1991 p. 21 to 22, entitled “A low-voltage triggering SCR for on-chip ESD protection at output and input pads” by Chatterjee, A., Polgreen, T. The SCR type ESD protection device can allow a larger current to flow through it as compared with a protection device which uses an MOSFET.
The SCR-used ESD protection device is composed of an SCR which lets the electrostatic current flow and escape outside and a trigger current supplying circuit (hereinafter also simply called “trigger circuit”) for latching the SCR. When a voltage to be applied to the trigger circuit exceeds a given value, the current starts to flow through the circuit. Various types of trigger circuits including the one that uses an NMOSFET have been devised.
The following will discuss first prior art which is an ESD protection device using a PN diode as the trigger current supplying circuit.
FIG. 1
is a plan view showing the ESD protection device according to the first prior art,
FIG. 2
is a cross-sectional view along line B-B′ in FIG.
1
and
FIG. 3
is an equivalent circuit diagram of the conventional ESD protection device. As shown in
FIGS. 1
to
3
, a P
+
substrate
101
of P
+
silicon is provided in the ESD protection device. An epitaxial layer
102
of P
−
silicon is formed on the P
+
substrate
101
. An N well
104
is formed in the top surface of the epitaxial layer
102
and a P well
103
is formed in contact with the N well
104
in such a way as to surround the N well
104
. A P
+
diffusion region
106
, an N
+
diffusion region
107
and a P
+
diffusion region
110
are formed on the top surface of the P well
103
and a P
+
diffusion region
108
and an N
+
diffusion region
109
are formed on the top surface of the N well
104
.
As shown in
FIG. 1
, the P
+
diffusion region
106
, the N
+
diffusion region
107
, the P
+
diffusion region
108
, the N
+
diffusion region
109
and the P
+
diffusion region
110
are laid out in line in the named order as seen from the direction that is perpendicular to the surface of the P
+
substrate
101
. Each diffusion region has a rectangular shape whose lengthwise direction is orthogonal to the layout direction of the individual diffusion regions. That is, the individual diffusion regions are laid out in parallel to one another. The lengths of the individual diffusion regions in the lengthwise direction are equal to one another. Further, a device isolation region
111
is formed in those regions of the top surface of the epitaxial layer
102
which exclude the individual diffusion regions.
As shown in
FIGS. 2 and 3
, the P
+
diffusion region
108
, the N well
104
and the P
+
substrate
101
form a vertical PNP bipolar transistor
114
and the N well
104
, the P well
103
and the N
+
diffusion region
107
form a horizontal NPN bipolar transistor
115
. The P well
103
is connected to the P
+
substrate
101
via the epitaxial layer
102
. With this structure, the base (N well
104
) of the vertical PNP bipolar transistor
114
and the collector (N well
104
) of the horizontal NPN bipolar transistor
115
are common to each other and the emitter (P
+
substrate
101
) of the vertical PNP bipolar transistor
114
and the base (P well
103
) of the horizontal NPN bipolar transistor
115
are connected together. Further, the P
+
diffusion region
108
, the N well
104
, the P well
103
and the N
+
diffusion region
107
form a PNPN SCR and the P
+
diffusion region
108
serves as the anode of this SCR while the N
+
diffusion region
107
serves as the cathode of the SCR.
An input pad
112
is connected to the P
+

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