Electrostatic discharge protection device

Details Electrostatic discharge protection device Electrostatic discharge protection device

2002-05-09

2003-09-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S350000, C257S372000

Reexamination Certificate

active

06621133

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrostatic discharge protection (ESD) device. More particularly, the present invention relates to an electrostatic discharge protection device fabricated through a complementary metal-oxide-semiconductor (CMOS) process that can be uniformly triggered during an electrostatic discharge.
2. Description of Related Art
Electrostatic discharge is a phenomenon triggered by movement of static charges along a non-conducting surface. In general, an electrostatic discharge may produce serious damages to the semiconductors and other circuit components inside an integrated circuit. People walking on a carpet may generate a few hundred to a few thousand volts of static electricity even if the surrounding atmosphere has a high relative humidity. If the surrounding relative humidity is low, a static electricity up to ten thousand or more volts may be produced. Integrated circuit packaging machines or integrated circuit testing equipment may also generate static electricity from several hundred to several thousand volts too. When a charged body (such as the human body, machine or equipment) touches a silicon chip, static charges may discharge through the chip. The power produced by such transient electrostatic discharge may permanently damage the circuits inside the chip or render a loss in function of some of the devices.
To prevent damage to integrated circuits due to electrostatic discharge, various types of electrostatic discharge protection devices are introduced.
FIG. 1
is a top view showing a conventional electrostatic discharge protection device.
FIG. 2
is a cross-sectional view along line I-I′ of FIG.
1
. As shown in
FIGS. 1 and 2
, the conventional electrostatic discharge (ESD) protection device has a multi-finger structure. The ESD protection device is formed on a P-type substrate
10
. The device comprises a metal-oxide-semiconductor (MOS) transistor region
100
, a guard ring
30
and a shallow trench isolation (STI) region
32
.
The MOS transistor region
100
accommodates a plurality of N-type metal-oxide-semiconductor (NMOS) transistors that includes a plurality of gate structures
12
,
14
,
16
,
18
as well as a plurality of source terminals
20
,
24
,
28
and a plurality of drain terminals
22
,
26
in the substrate
10
on each side of the gate structures
12
,
14
,
16
and
18
. The source terminal
20
is the emitter of a parasitic bipolar junction transistor (parasitic BJT)
110
and the drain terminal
22
is the collector of the parasitic BJT
100
. The substrate
10
between the source terminal
20
and the drain terminal
22
is the base of the parasitic BJT
110
. The source terminal
24
is the emitter of a parasitic bipolar junction transistor
112
and the drain terminal
24
is the collector of the parasitic BJT
1
12
. The substrate
10
between the source terminal
24
and the drain terminal
22
is the base of the parasitic BJT
112
. The source terminal
24
is the emitter of a parasitic bipolar junction transistor
114
and the drain terminal
26
is the collector of the parasitic BJT
114
. The substrate
10
between the source terminal
24
and the drain terminal
26
is the base of the parasitic BJT
114
. Similarly, the source terminal
28
is the emitter of a parasitic bipolar junction transistor
116
and the drain terminal
26
is the collector of the parasitic BJT
116
. The substrate
10
between the source terminal
28
and the drain terminal
26
is the base of the parasitic BJT
116
.
The guard ring
30
is a circumscribing P+-doped region around the substrate
10
. The guard ring
30
is connected to a ground (not shown). The guard ring
30
is isolated from the MOS transistor region
100
through shallow trench isolation (STI) regions
32
. The source terminals
20
,
24
,
28
are also connected to the ground. The drain terminals
22
and
26
are connected to an input terminal (not shown).
However, for this type of ESD protection device, the device may be triggered non-uniformly during an electrostatic discharge. In other words, the parasitic BJTs
112
,
114
near the central portion of the device may be turned on before the other parasitic BJTs
110
and
116
. This occurs because the equivalent resistance of the base terminal for each of the parasitic transistors
110
,
112
,
114
and
116
may be different. That means, the parasitic BJTs
112
and
114
near the central portion of the device have a higher equivalent base resistance and hence open more readily. The two parasitic BJTs
110
and
116
on each side of the device have to open later due to a lower equivalent base resistance. In general, a BJT having a larger opening area has a higher electrostatic discharge capacity. Since the region having the maximum opening lies in the central portion of a conventional ESD protection device, such uneven opening across the device often leads to a drop in ESD capacity. ESD protection capacity is particularly compromised if the device occupies a large surface area.
To switch on all the parasitic BJTs within an ESD protection device concurrently, a number of improvements to the structure of the ESD protection device have been introduced.
FIG. 3
is a top view of a conventional electrostatic discharge protection device having an improved structure for countering non-uniform switching of parasitic devices.
FIG. 4
is a cross-sectional view along line II-II′ of FIG.
3
.
As shown in
FIGS. 3 and 4
, the device includes a metal-oxide-semiconductor (MOS) transistor region
100
, a guard ring
30
, a shallow trench isolation (STI) region
32
and a longitudinal P+-doped region
30
a
over a P-type substrate
10
. The gate terminals
12
,
14
,
16
,
18
, the source terminals
20
,
24
,
28
and the drain terminals
22
,
26
have been described with reference to
FIGS. 1 and 2
and hence their description is omitted.
In this device, aside from having the guard ring
30
circumscribing the substrate
10
, a longitudinal P+-doped region
30
a
is inserted into the mid-section of the source terminal
24
. Hence, the source terminal
24
is divided into two source terminals,
24
a
and
24
b
. In addition, the STI region
32
is positioned at each end of the substrate
10
isolating the guard ring
30
from the MOS transistor region
100
.
The design of this type of ESD protection device relies on connecting all the source terminals
20
,
24
a
,
24
b
and
26
of the MOS transistors within the device with a ground (the guard ring
30
and the longitudinal P+-doped region
30
a
). Thus, all the parasitic BJTs
110
,
112
,
114
,
116
within the ESD protection device are triggered concurrently to produce an optimal discharging effect. Nevertheless, in deep sub-micron fabrication, design of the longitudinal P+-doped region
30
a
lowers the base resistance of the parasitic BJTs
110
,
112
,
114
,
116
so that the parasitic BJTs
110
,
112
,
114
and
116
are difficult to trigger hence reducing ESD capacity of the device.
In addition, the concentration of dopants in P-type and N-type wells will increase when integrated circuits are fabricated in the deep sub-micron regime. Since the equivalent base resistance of the parasitic BJTs within the ESD protection device is dependent on the resistance in the well region, triggering of the parasitic BJTs is increasingly difficult. Although the aforementioned method is capable of improving non-uniform triggering of parasitic BJTs, difficult triggering of the ESD protection device compromises its protective capacity.
Another method of improving non-uniform switching of a conventional ESD protection device is to set up special electronic circuits. Gate driven or substrate-triggered circuits are sometimes incorporated into the ESD protection device, but this type of design requires additional circuit layout leading to greater circuit complexity as well as an increase in production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to pro

Affiliated with

Also associated with

Rating

Electrostatic discharge protection device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3079266