Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-25
2003-09-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000
Reexamination Certificate
active
06617650
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an electrostaticdischarge (ESD) protection circuit. More particularly, the present invention relates to a structure of an electrostaticdischarge protection device having an open base parasitic bipolar transistor for reducing substrate leakage current. The electrostaticdischarge protection device according to the present invention is compatible with standard Bipolar/BiCMOS manufacturing processes and SiGe-BiCMOS manufacturing processes.
2. Description of the Prior Art
It has been known that extremely high voltages (e.g. 10,000 volts or greater) can develop in the vicinity of an integrated circuit (IC) due to the build-up of static charge. Electrostatic discharge (ESD) refers to the phenomenon whereby an electrical discharge of high current and short duration is produced at the package nodes of an integrated circuit, as a consequence of static charge build-up on that IC package or on a nearby body such as a human being or an IC handling machine. Electrostatic discharge is a serious problem for semiconductor devices since it has the potential to disable or destroy the entire integrated circuit. Because ESD events occur most often across the silicon circuits attached to the package nodes, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits. Ideally, an ESD protection device should be able to protect an IC against any conceivable static discharge by passing large currents in a short time in a nondestructive manner.
Diode strings have been used to couple peripheral power supplies to their corresponding core power supplies during ESD events. A typical example of a diode string would be a Vsso (e.g., a noisy output supply) double-clamped to core, or substrate, Vss. It is also known that the diode strings can be used in ESD protection between power pads (e.g. between Vcc
1
and Vcc
2
; or between Vss
1
and Vss
2
) or trigger circuit design.
FIG. 1
is a cross-sectional view of a conventional diode clamp structure, which is made up of four diodes coupled in series. The diode is shown consisting of a set of separate structures disposed in substrate
10
. Each diode structure includes a P
+
diffusion region and a N
+
diffusion region (P
+
:
3
a
~
3
d
and N
+
:
4
a
~
4
d
, respectively) disposed in a floating N-well (
9
a
~
9
d
, respectively). Each of the four separate N-well regions
9
a
~
9
d
are formed in P-type substrate
10
. By way of example, the first diode in the series comprises diffusion regions
3
a
and
4
a
, with P
+
diffusion region
3
a
being coupled to a drain voltage V
D
or a peripheral power supply Vccp.
The series connection of separate diodes, which comprise the diode clamp, are coupled together using any available metal layer. The metal connections are always from the N
+
region of the previous diode stage to the P
+
region of the next stage; that is, N
+
region
4
a
is coupled to P
+
region
3
b
, N
+
region
4
b
is coupled to P
+
region
3
c
, and so on. At the cathode terminal of the diode clamp, N
+
region
4
d
is grounded or coupled to an internal power supply Vcc.
The diode strings are designed to provide a current path during an electrostatic discharge event. However, the above-described prior art diode string structure suffers from a serious substrate leakage current problem. Referring to the first diode in the series of diode string illustrated in
FIG. 1
, by way of example, the substrate leakage current I
sub
(I
sub
=I
D
×&bgr;/(1+&bgr;), where &bgr; is the current gain) occurs due to a parasitic PNP bipolar transistor consisting of the P
+
junction
3
a
, the N well
9
a
, and the P-type substrate
10
. When the number of the diodes (or stages of the diode string) increase, the leakage gets worse. A total substrate leakage current I
sub, total
of a four-stage diode string as set forth in
FIG. 1
can be expressed by the following equation:
I
sub, total
=I
D
×&bgr;(1/(1+&bgr;)+1/(1+&bgr;)
2
+1/(1+&bgr;)
3
+1/(1+&bgr;)
4
)
where I
D
is the input current through the anode P
+
junction
3
a
and &bgr; is the current gain. Furthermore, a diode device having a relatively low leakage current when operated below a turn on voltage thereof is desired.
Accordingly, there is a strong need to provide an improved diode structure and a diode string thereof having reduced substrate leakage current during operations.
SUMMARY OF INVENTION
The primary objective of the present invention is to provide an electrostatic discharge (ESD) protection device, which is compatible with standard Bipolar/BiCMOS manufacturing processes and has low leakage.
Another objective of the present invention is to provide a diode device and a diode string thereof for an ESD protection circuit. The diode device according to the present invention has an open base parasitic PNP bipolar transistor, resulting in reduced substrate leakage current of the diode string.
Still another objective of the present invention is to provide a low-leakage ESD protection diode device that is applicable to power clamp circuits, ESD protection circuit between power pads, or trigger circuit design.
In accordance with the claimed invention, a diode device for an electrostaticdischarge (ESD) protection circuit includes a P-type substrate, a buried N
+
heavily doped semiconductor layer implanted in the P-type substrate and bounded by a deep trench isolation, a P well disposed above the buried N
+
heavily doped semiconductor layer in the P-type substrate and isolated from the P-type substrate by the deep trench isolation. A P
+
doped region, which serves as an anode of the diode device, is located in the P well. A N
+
doped region, which serves as a cathode of the diode device, is laterally disposed in the P well and spaced apart from the P
+
doped region. The P
+
doped region, the buried N
+
heavily doped semiconductor layer, and the P-type substrate constitute an open base parasitic PNP bipolar transistor.
REFERENCES:
patent: 5324982 (1994-06-01), Nakazato et al.
patent: 6462380 (2002-10-01), Duvvury et al.
patent: 6492208 (2002-12-01), Cheng et al.
Chen Shiao-Shien
Chou Chiu-Hsiang
Tang Tien-Hao
Hsu Winston
Meier Stephen D.
United Microelectronics Corp.
LandOfFree
Electrostatic discharge protection device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrostatic discharge protection device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3008304