Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1998-12-03
2001-01-02
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Utility Patent
active
06169310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit elements and, in particular, to electrostatic discharge (ESD) protection devices for use in integrated circuits and processes for their manufacture.
2. Description of the Related Art
Electrostatic discharge (ESD) protection devices are commonly connected to individual input and output pads of integrated circuits to protect electronic devices in the integrated circuit from excessive voltage. See, for example, S. M. Sze,
Electrostatic Discharge Damage
in
VLSI Technology, Second Edition,
648-650 (McGraw Hill, 1988), which is hereby incorporated by reference.
A variety of conventional ESD protection devices are also known which can provide a path, between a pair of normally isolated input and/or output pads, that becomes electrically conductive when the voltage differential across the pair of pads exceeds a predetermined value. Such conventional ESD protection devices make extensive use of diodes (often in the avalanche multiplication regime), metal-oxide-semiconductor (MOS) transistors (typically in the punch-through regime) and bipolar transistors (usually in punch-through mode). Since the electrical characteristics of diodes and MOS and bipolar transistors are, however, extremely device and manufacturing technology dependent, integrated circuits which employ these ESD protection devices often must be redesigned and recharacterized for each successive technology generation. In addition, conventional ESD protection devices typically do not protect electronic devices within the integrated circuit from ESD events which occur at the V
dd
and V
ss
pads.
Still needed in the art is an ESD protection device that provides protection to devices within an integrated circuit from ESD events at any pad, including V
dd
and V
ss
, and that does not rely on technology dependent diodes or transistors.
SUMMARY OF THE INVENTION
The present invention provides an ESD protection device for use with an integrated circuit that creates a near “short circuit” (i.e. a low impedance resistive path) between IC pads (including V
dd
and V
ss
pads) when power to the IC is off, while assuring adequate isolation between IC pads when the power is on.
Electrostatic discharge (ESD) protection devices according to the present invention can be used in association with integrated circuits that have a power supply and a plurality of pads connected to each other via a current dissipating means. The ESD protection device in accordance with the present invention includes a semiconductor substrate of a first conductivity type (typically p-type) with an active area on its surface, and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the two vertically integrated pinch resistors includes a deep well region of a second conductivity type (typically n-type) disposed below both the semiconductor substrate surface and the active area, as well as a first surface well region of the second conductivity type (e.g. n-type) disposed on the surface of the semiconductor substrate. The first surface well region circumscribes (i.e. encircles) both the deep well region and the active area of the semiconductor substrate, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) in the semiconductor substrate. This narrow channel region separates the deep well region from the first surface well region. Each of the vertically integrated pinch resistors also includes a first contact region in the first surface well region, that is connected to the power supply of the integrated circuit, a second contact region in the active area, that is connected to a pad of the integrated circuit, and a third contact region in the semiconductor substrate, that is connected to the electrical discharge line.
When no potential is applied on the first contact regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line of the ESD protection device according to the present invention provide a low impedance resistive path between the pads. When a potential is applied to the first contact regions by means of the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region extending from the first surface well region into the narrow channel region toward the deep well region, thereby isolating the pads from each other.
A process for the formation of an ESD protection device according to the present invention includes first providing a semiconductor substrate of a first conductivity type (e.g. a p-type silicon substrate), followed by forming a plurality of deep well regions of a second conductivity type (e.g. n-type) embedded below its surface. Next, at least one electrical isolation region is formed on the surface of the semiconductor substrate above the deep well regions. A plurality, which is typically the same number as the number of the deep well regions, of surface well regions of the second conductivity type is then formed on the surface of the semiconductor substrate such that each of the first surface well regions circumscribes a different deep well region. A first contact region is subsequently formed on the surface of each of the first surface well regions. Next, a plurality of second contact regions are formed on the surface of the semiconductor substrate, each above a different deep well region, and a plurality of third contact regions are formed on the surface of semiconductor substrate, each outside of a perimeter formed by a different first surface well region. The first contact region, second contact region and third contact region are formed in such a manner that they are separated by the electrical isolation regions. Finally, an electrical discharge line, connected to and in common with all the third contact regions, is formed, as well as connections between the power supply of the IC and the first contact regions, and between a plurality of pads of the IC and the associated second contact regions. The resultant device includes a plurality of vertically integrated pinch resistors, each of which is connected to an electrical discharge line and a pad of the IC.
REFERENCES:
patent: 4266100 (1981-05-01), Hoppner et al.
patent: 4725876 (1988-02-01), Kishi
patent: 4947226 (1990-08-01), Huang et al.
patent: 5079516 (1992-01-01), Russell et al.
Bertram, W. J.; Yield and Reliability, VLSI Technology, 2 Ed., pp. 648-650 (S.M. Sze Ed.), McGraw-Hill (1988).
Bergemont Albert
Kalnitsky Alexander
Lin Hengyang (James)
Poplevine Pavel
Limbach & Limbach LLP
Meier Stephen D.
National Semiconductor Corporation
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