Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-16
2002-06-25
Meier, Stephen D. (Department: 2836)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000
Reexamination Certificate
active
06410963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electrostatic discharge protection circuit, and particularly relates to electrostatic discharge protection circuit with latch-up prevention function.
2. Description of the Prior Art
To prevent integrated circuits is damaged by large current or larger voltage, such as to prevent integrated circuits is damaged by large current induced by noise or insulation failure. As
FIG. 1A
shows, most of current integrated circuits not only have interface terminal
11
, such as pad, for inputting and/or outputting and devices area
12
, where numerous electronic devices locate, but also electrically couple electrostatic discharge protection circuit
13
with both interface terminal
11
and devices area
12
. On normal times, electrostatic discharge protection (ESD) circuit
13
is off. In contrast, whenever voltage of external signal, which appears in interface terminal
11
, is larger than the triggering voltage of electrostatic discharge protection circuit
13
, electrostatic discharge protection circuit
13
is turned-on to conduct this external signal to ground point
13
, such that devices area
12
is not affected by this external signal. Of course, to avoid devices area
12
is affected by this external signal before electrostatic discharge protection circuit
13
is turned-on, buffer area
15
, which is turned-on slowly than electrostatic discharge protection circuit
13
, is broadly located between interface terminal
11
and devices area
12
.
Although numerous electrostatic discharge protection circuits are available, silicon controlled rectifier (SCR) is the most efficient of all available ESD circuits in terms of ESD performance per unit. SCR essentially consists of a PNPN structure, as shown in
FIG. 1B
, both first N-type doped region
16
, which locates in N-type well
193
, and first P-type doped region
17
are electrically coupled with interface terminal
11
, second N-type doped region
18
and second P-type doped region
19
, both directly locate in P-type substrate
196
, are electrically coupled with ground point
14
. Equivalent circuit of SCR consists of two reciprocally electrically coupled bipolar junction transistors, as
FIG. 1C
shows. Where first bipolar junction transistor T
1
is made from first P-type doped region
17
, N-type well
193
, and P-type substrate
196
, second bipolar junction transistor T
2
is made from N-type well
193
, P-type substrate
196
, and second N-type doped region
18
, two resistors R
1
and R
2
indicate resistance of P-type substrate
196
and resistance of N-type well
193
separately.
Obviously, after this voltage interface terminal
11
applies on first P-type doped region
17
and first N-type doped region
16
exceeds breakdown voltage of (V
BD
) N-type well
193
, numerous electron-hole pairs are formed. Herein, electrons flow through R
2
(resistance of N-type well) and N-type doped region
16
into a high voltage point, and holes flow through R
1
(resistance of p-type well) and P-type doped region
19
into a low voltage point. And then, a voltage drop is formed while electrons flow through R
2
and holes flow through R
1
, and bipolar junction transistors T
1
and T
2
would be turned on while this voltage is large enough. Because turn-on of each bipolar junction transistor, such as T
1
, would drive current through resistance, such as T
1
, and further increases this voltage drop, another bipolar junction transistor, such as T
2
, would be further turned-on. A positive feedback loop is formed and a direct result is that SCR is turned-on while a small voltage appears on interface terminal
11
. In general, symbol Vtrig indicates the voltage that both bipolar junction transistors are turned on and symbol Itrig indicates corresponding current, and symbol Vh indicates minimum voltage for maintaining SCR being turned-on.
Because triggering voltage decides when ESD protection circuit insulate external signal(s) from devices area
12
, it is better to let triggering voltage is briefly equal to work voltage (Vdd) of device area (or the summation of work voltage and a predetermined safety range), to ensure no high voltage external signal flow into devices area
12
. In general, triggering voltage of ESD protection circuit could be reduced by following modifications, but all modifications still use two bipolar junction transistors. As
FIG. 2A
shows, additional N-type doped region
21
is formed between first P-type doped region
17
and second N-type doped region
18
to let SCR could be operated while electrical breakdown between additional N-type doped region and P-type substrate is happened, and leakage current is reduced for lower breakdown voltage. As
FIG. 2B
shows, both additional N-type region
21
and controlling gate
22
, which electrically couple with ground point, are formed at edge of N-type well
193
to form a gated-diode, where voltage required to turn-on this gated-diode is smaller than voltage to turn-on both bipolar junction transistors. As
FIG. 2C
show, replace additional N-type region
21
by additional P-type region
23
, and form controlling gate
24
which electrically coupled with interface terminal
11
but not gate
22
which electrically coupled with ground point
14
, such that triggering voltage of SCR is reduced while lower breakdown voltage between additional P-type region
23
and N-type well
193
. More discussions about ESD protection circuit with SCR could be acquired by referring this book: ESD IN SILICON INTEGRATED CIRCUITS, ISBN 0-741-95481-0.
However, if interface terminal continuously provide voltage, which is larger than Vh, after both bipolar junction transistors are turned-on, ESD protection circuit would be always turned-on. In the meantime, latch-up phenomena would be happened. Reasonable, whenever integrated circuits is not operated after latch-up phenomena is happened, lowered triggering voltage of ESD protection circuit does not induce any serious damages. In contrast, whenever integrated circuits is operated again after latch-up phenomena is happened, if voltage of normal signal between interface terminal and device area exceeds Vh, this signal would be conducted to ground point after SCR is turned-on by turned-on ESD protection circuit, such that integrated circuits could not properly operate.
Certainly, a direct solution of this problem is to modify configuration of ESD protection circuits with SCR to let Vh is obviously larger than voltage of normal signal, or increases corresponding Itrig and Vtrig. However, because modification of ESD protection circuit also affects V
BD
. Vtrig, and Itrig, quality of ESD protection circuit with SCR also would be affected. Thus, latch-up phenomena still is an urgent problem.
SUMMARY OF THE INVENTION
One main object of this invention is to present an ESD protection circuits with SCR which has the ability to reduce or even eliminate latch-up phenomena.
One preferred embodiment of this invention is an electrostatic discharge protection which is electrically coupled with an interface terminal and a devices area, at least include a first bipolar junction transistor, a second bipolar junction transistor, a first MOS transistor (metal-oxide-semiconductor transistor), and a second MOS transistor. Both bipolar junction transistors forms the well-known silicon controlled rectifier, first MOS transistor locates between interface terminal and base of second bipolar junction transistor (collector of first bipolar junction transistor), and second MOS transistor locates between base of second bipolar junction transistor and ground point, and gates of both MOS transistor electrically coupled with voltage base point whose voltage is equal to work voltage of devices area. While devices area is turned off, silicon controlled rectifier provides function of electrostatic discharge protection and maybe latch-up. While devices area is turned on, second MOS transistor also is turned on so that part of current flows into ground point but not flows into second bipolar
Lai Chen-Shang
Liu Meng-Huang
Lu Tao-Cheng
Su Shin
Macronix International Co. Ltd.
Meier Stephen D.
LandOfFree
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