Electrostatic discharge protection circuit using triple...

Details Electrostatic discharge protection circuit using triple... Electrostatic discharge protection circuit using triple...

2005-12-05

2008-03-11

Gurley, Lynne (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S107000, C257S132000, C257S133000, C257S134000, C257S173000, C257S213000, C257S288000, C257S358000, C257S360000, C257S361000, C257SE27033, C257SE27063, C257SE29225, C361S056000, C361S091500, C361S111000

Reexamination Certificate

active

07342281

ABSTRACT:
Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

REFERENCES:
patent: 5576557 (1996-11-01), Ker et al.
patent: 6768616 (2004-07-01), Mergens et al.
“A Novel Gate-Coupled SCR ESD Protection Structure With High Latchup Immunity for High-Speed I/O Pad,” Chun-Hsiang Lai et al, IEEE Electron Device Letters, vol. 25, No. 5, May 2004, pp. 328-330, © 2004 IEEE.

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