Electrostatic discharge protection circuit triggered by capaciti

Details Electrostatic discharge protection circuit triggered by capaciti Electrostatic discharge protection circuit triggered by capaciti

1996-06-28

1997-11-11

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257355, 257360, H01L 2362

Patent

active

056867514

ABSTRACT:
An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load. The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V.sub.SS /V.sub.DD. A gate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor. The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V.sub.SS /V.sub.DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

REFERENCES:
patent: 4246502 (1981-01-01), Kubinec
patent: 4261772 (1981-04-01), Lane
patent: 4441249 (1984-04-01), Alspector et al.
patent: 5086365 (1992-02-01), Hen
patent: 5286992 (1994-02-01), Ahrens et al.
patent: 5337279 (1994-08-01), Gregory et al.
patent: 5486716 (1996-01-01), Saito et al.

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