Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-15
2001-01-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S357000
Reexamination Certificate
active
06172403
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrostatic discharge protection techniques for semiconductor integrated circuitry. More particularly, the present invention relates to an electrostatic discharge protection circuit triggered by a floating-base transistor.
2. Description of the Related Art
Electrostatic discharge, ESD hereinafter, may occur everywhere during the phases of testing, assembly, installation, operation, etc., and cause damage to integrated circuits (ICs). Nowadays, several models have been propounded to simulate ESD events, wherein a so-called Human Body Model is generally used to evaluate ESD immunity for integrated circuits because it has a longer ESD pulse period.
Sub-micron CMOS ICs have become increasingly vulnerable to ESD damage due to advanced processes, such as the use of lightly-doped drain structures and clad silicide diffusions. Conventionally, lateral silicon-controlled rectifiers (LSCRs) have been disclosed (for example, in U.S. Pat. No. 5,012,317) as ESD protection circuits for shunting ESD stress. However, the triggering of the conventional lateral silicon-controlled rectifier to activate and thus bypass the ESD stress relies heavily on the P/N junction breakdown between a substrate and a well region formed therein. Due to the fact that both of the substrate and well region are generally provided with a low doping concentration, the trigger voltage of the lateral silicon-controlled rectifier can be up to 30V or more, at which point the ICs may have been adversely affected.
To lower the trigger voltage, U.S. Pat. No. 5,465,189 has disclosed “A LOW VOLTAGE TRIGGERING SEMICONDUCTOR CONTROLLED RECTIFIER” as illustrated in FIG.
1
. In the drawing, the SCR is fabricated onto a P-type semiconductor substrate
10
, in a predetermined portion of which an N-well region
11
is formed. A P-type doped region
12
and an N-typc doped region
13
are formed within the extent of the N-well region
11
and spaced apart from each other, while an N-type doped regions
14
and a P-type doped region
15
are formed within the extent of the P-type semiconductor substrate
10
and spaced apart from each other. The P-type doped region
12
and the N-type doped region
13
are connected together to an IC pad
1
. The IC pad
1
is electrically connected to an internal circuit
2
, which is vulnerable to ESD damage and should be protected by the lateral silicon-controlled rectifier. In addition, the N-type doped region
14
and the P-type doped region
15
are connected together to a potential node V
SS
, which is generally connected to a ground under normal operation.
Moreover, an N-type doped region
16
is a heavily-doped region, having one portion formed in the N-well region
11
and another portion formed in the P-type semiconductor substrate
10
. In other words, the N-type doped region
16
stretches across the P/N junction between the N-well region
11
and the P-type seumconductor substrate
10
. Furthermore, a gate structure
17
for this conventional ESD protection circuit is provided from bottom to top, with a gate dielectric layer
18
and a gate electrode layer
19
connected to the V
SS
node to overlie a portion of the semiconductor substrate
10
between the N-type doped region
14
and
16
.
Correspondingly, the P-type doped region
12
, the N-well region
11
, and the P-type semiconductor substrate
10
serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor
20
, while the N-well well region
11
, the P-type semiconductor substrate
10
, and the N-type doped region
14
serve as the collector, base, and emitter, respectively, of an NPN bipolar junction transistor
21
. Referring to
FIG. 2
, the equivalent circuit diagram of the conventional lateral silicon-controlled rectifier of
FIG. 1
is schematically depicted. In the drawing, resistors
22
and
23
designate the respective spreading resistance of the N-well region
11
and the P-type semiconductor substrate
10
. Reference numeral
24
represents a metal-oxide-semiconductor field-effect transistor (MOSFET) constituted by the N-type doped regions
14
and
16
, the portion of the semiconductor substrate
10
there between, and the gate structure
17
.
The conventional ESD protection circuit shown in
FIG. 1
has a relatively low trigger voltage but consumes a greater amount of layout area. Moreover, as integrated circuit fabrication advances into the deep sub-micron era, the resistance of the substrate is decreasing, making it more difficult for ESD protection circuits to be triggered.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an electrostatic discharge protection circuit triggered by a floating-base transistor at a decreased trigger voltage suitable for deep sub-micron ICs.
It is another object of the present invention to provide an electrostatic discharge protection circuit occupying less layout area.
The present invention achieves the above-indicated objects by providing an electrostatic discharge protection circuit triggered by a transistor having a floating base. The electrostatic discharge protection circuit comprises: an N-type semiconductor layer, a floating P-type semiconductor layer, a first P-type doped region, a first N-type doped region, a second N-type doped region, and a third N-type doped region. The floating P-type semiconductor layer is in contact with the N-type semiconductor layer so as to establish a junction there between. The first P-type doped region and the first N-type doped region are formed in the N-type semiconductor layer, both of which are connected to a first node. The second N-type doped region is formed in the P-type semiconductor layer and connected to a second node, while the third N-type doped region spans the junction. In addition, there is formed a gate structure overlying a portion of the P-type semiconductor layer between the second and third N-type doped regions.
According to the present invention, the lateral silicon-controlled rectifier provided with an NPN bipolar junction transistor having a floating base can be triggered at a decreased voltage while consuming less layout area.
REFERENCES:
patent: 5012317 (1991-04-01), Rountre
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5719733 (1998-02-01), Wei et al.
patent: 5742084 (1998-04-01), Yu
patent: 5856214 (1999-01-01), Yu
patent: 5932916 (1999-08-01), Jurg
patent: 6066879 (2000-05-01), Lee et al.
Ladad & Parry
Meier Stephen D.
Winbond Electronics Corp.
LandOfFree
Electrostatic discharge protection circuit triggered by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrostatic discharge protection circuit triggered by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection circuit triggered by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2490350