Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-06
2003-07-29
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S360000
Reexamination Certificate
active
06600198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device including a silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for a high frequency, which has high resistance against occurrence of surges such as a discharge phenomenon, as well as a method of manufacturing the same.
2. Description of the Background Art
As a result of widespread use of cellular phones and practical use of wireless LAN (Local Area Network) in recent years, attention has been focused on high-frequency semiconductor devices, which are essential for achieving high performance, small sizes and low costs of such electronic devices. In many cases, materials of these high-frequency semiconductor devices are III-V semiconductors such as GaAs having a high electron mobility. In recent years, however, the sizes of silicon MOS transistors have been remarkably reduced to allow production of MOS transistors having gate lengths shorter than 0.2 &mgr;m. The silicon MOS transistor having such a minute gate length can be applied to a high-frequency device in a gigahertz band because a trans-conductance Gm is remarkably improved and high-frequency characteristics are improved. However, the silicon MOS transistor having a gate length, which is reduced for use in a high-frequency device, has a lower resistance against a surge than conventional elements employing GaAs or the like. Therefore, it is necessary to take countermeasures against occurrence of surges such as electrostatic discharge.
Then, the countermeasures against disturbances such as electrostatic discharge will be described. When an electrostatically charged object comes into contact with another object, a discharge phenomenon may occur between these objects. This discharge phenomenon is called “ESD (ElectroStatic Discharge)”. When ESD occurs in a semiconductor element, it may damage the semiconductor element. As typical models of the ESD, there are three models, i.e., (a) HBM (Human Body Model) which is a model of discharge from a charged human body to a semiconductor element, (b) MM (Machine Model) which is a model of discharge from a charged device to a semiconductor element and (c) CDM (Charge Device Model) which is a model of a phenomenon of discharge of electric charges carried on a semiconductor element itself to a grounded object. Among them, examples of current waveforms in (a) HBM and (c) CDM are shown in FIG.
59
. It can be seen from
FIG. 59
that a current stress of about 1 A occurs for a relatively long time of 100 ns in HBM, but a high current stress of about 10 A occurs for a very short time of 1 ns in CMD. In either of these models, a high current flows for a short time.
As described above, when ESD occurs, a high current is applied to the semiconductor element for a short time so that thermal destruction, i.e., melting by Joule heat, occurs. Further, insulation breakdown has occurred in some cases employing MOS transistor structures, which have been in the mainstream of LSI (Large-Scale Integration) silicon devices in recent years, because a high electric field due to ESD is applied to a gate oxide film of the MOS transistor. This insulation breakdown of the gate oxide film caused by ESD causes a significant obstacle to utilization of an inexpensive silicon semiconductor member. Countermeasures have been employed for avoiding the insulation breakdown of the gate oxide film. According to the countermeasures, an appropriate kind of protection circuit is formed between an I/O pin and an internal circuit so that a high-voltage surge caused upon occurrence of ESD may not reach the internal circuit. This protection circuit is called an ESD protection circuit. An object or target on a silicon wafer, which is connected to the foregoing I/O pin by wire bonding, is a pad. In the following description, therefore, a term “I/O pad” is used instead of “I/O pin”.
In many cases, the ESD protection circuit is formed of a circuit, in which an MOS transistor in the off state is connected to an I/O signal line (M. -D. Ker et al., IEDM, pp. 889-892, 1996).
FIG. 60
is a circuit diagram showing a semiconductor device, in which an MOS transistor in the off state is used as the ESD protection circuit. In
FIG. 60
, an n-channel MOS transistor
117
n
(which may be referred to as an “nMOS” hereinafter) and a p-channel MOS transistor
117
p
(which may be referred to as a “pMOS” hereinafter) are off. The nMOS has a drain D connected to an I/O signal line, and also have a gate G, a source S and a p-conductive well (which will be referred to as a “p-well” hereinafter) W, which are all grounded. The pMOS has a drain D connected to the I/O signal line, and also have a gate, a source and an n-well all connected to an external supply voltage, which will be referred to as “Vdd” hereinafter. Since two MOS transistors
117
p
and
117
n
are off, these transistors do not pass any current during an ordinary operation, and do not affect ordinary device operations.
When a high-voltage surge due to ESD is applied through the I/O pad, parasitic bipolar transistor effects occur in the pMOS and nMOS as described below so that a path for a high current flow from the drain to the source is formed.
FIG. 61
shows the parasitic-bipolar transistor effect of the MOS transistor. In the following description, it is assumed that a surge of a positive voltage is applied to the drain of the nMOS. First, the positive voltage surge is applied to an n
+
-type diffusion layer of drain D formed at a silicon substrate
101
. When the voltage thus applied increases, breakdown occurs on a pn junction of the n
+
-type diffusion layer, which is reversely biased, so that large amounts of electrons and holes are produced by impact ionization. These electrons flow to drain D bearing a positive voltage, and these holes flow to grounded p-well W.
It is assumed that the flow of holes to the p-well causes a current of a magnitude of I
hole
, and the p-well has a resistance value of R
sub
. A voltage drop of I
hole
·R
sub
occurs in the direction of depth of the p-well. This voltage drop causes a potential difference in the p-well so that the potential in the p-well region located at a shallow position immediately under the nMOS gate rises to a positive potential. In this operation, the n
+
-type diffusion layer of the drain, the shallow p-well region immediately under the gate and the n
+
-type diffusion layer of the source form an npn parasitic bipolar transistor. In this npn parasitic bipolar transistor, a reverse bias voltage is applied to a junction between the n
+
-type diffusion layer of the drain and the shallow p-well region under the gate, and a positive bias voltage is applied to a junction between the shallow p-well region under the gate and the n
+
-type diffusion layer of the source. By these voltages, the parasitic npn bipolar transistor is turned on.
In summary, when ESD occurs and a positive voltage is applied to the drain of the nMOS, which has a grounded gate and is off, the npn parasitic bipolar transistor is turned so that a large current can flow.
When a surge of a negative voltage is applied to the drain of the pMOS, effects similar to the above occur. Further, when a positive voltage is applied to the drain of the pMOS, the junction between the drain and n-well of the pMOS is subjected to a forward bias, and a current flows to the n-well. The on-operation in this case is usually expected in the pMOS. When a surge of a negative voltage is applied to a drain of the nMOS, a forward bias state is likewise attained and a current flows to the p-well similarly to the pMOS. The on-operation thus performed is also expected usually in the nMOS.
As described above, the ESD protection circuit using the MOS transistors in the off state can relieve a large current to the GND (ground) or Vdd when ESD occurs. As a result, it is possible to prevent flow of a large current in an internal circuit so that thermal destr
Ohnakado Takahiro
Yamakawa Satoshi
Eckert George
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Electrostatic discharge protection circuit for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrostatic discharge protection circuit for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection circuit for a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3079564