Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-02
2001-04-10
Ngo, Ngan V. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000
Reexamination Certificate
active
06215157
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrostatic discharge protection circuit for a semiconductor integrated circuit such as a semiconductor memory device as well as a layout of the electrostatic discharge protection circuit.
The semiconductor integrated circuit such as dynamic random access memory device has a substrate potential which remains biased at the ground potential or a minus potential, wherein a bias line is used as a ground line for an internal circuit. This ground line extends through a semiconductor pellet or along an external shape of the pellet. This ground line is connected through the electrostatic discharge protection circuit to electrode pads. This ground line is also used as a common discharge line for application of an electrostatic voltage. Such conventional semiconductor integrated circuit is, for example, disclosed in Japanese laid-open patent publication No. 7-86510.
In recent years, scaling down of the semiconductor devices as integrated and an increase in integration of the semiconductor integrated circuit have been progressed. In advanced dynamic random access memory such as 64M-bits dynamic random access memory, the semiconductor substrate has three-layered wells and the substrate potential is fixed at the ground level. The conventional circuit configuration of the dynamic random access memory will be described.
FIG. 1
is a circuit diagram illustrative of a conventional circuit configuration including the electrostatic discharge protection circuit. A ground pad
101
is provided which is connected with a ground line
7
. The ground potential is given to the ground pad
101
by contacting a pin to the ground pad
101
externally. Electrode pads
102
,
103
,
104
and
105
are also provided which are connected to electrostatic discharge protection circuits. Those electrostatic discharge protection circuits are also connected to the ground line
7
. Those electrostatic discharge protection circuits are also provided between the electrode pads
102
,
103
,
104
and
105
and the ground line
7
. Each of the electrostatic discharge protection circuits comprises a diode
2
and a voltage clamping device
3
. This electrostatic discharge protection circuit is operated as follows.
If an electrostatic voltage which is higher in potential than the ground pad
101
is applied to the electrode pad
104
, then the voltage claming device
3
is made conductive to allow discharge from the ground pad
101
. If an electrostatic voltage which is lower in potential than the ground pad
101
is applied to the electrode pad
104
, then the diode
2
is made conductive to allow discharge from the ground pad
101
. The ground line
7
serves as a common discharge line.
The pad
103
serves as a signal input/output pad. This signal input/output pad is also connected to an n-channel output MOS field effect transistor
5
and a p-channel output MOS field effect transistor
6
. The n-channel output MOS field effect transistor
5
and the p-channel output MOS field effect transistor
6
form an inverter which serves as an output driving circuit (output buffer). An output signal from the semiconductor integrated circuit is inputted into gates of the n-channel output MOS field effect transistor
5
and the p-channel output MOS field effect transistor
6
, and further this signal is amplified and supplied to the signal input/output pad
103
. An input signal is applied to the signal input/output pad
103
and then transmitted through an input signal line represented by an arrow mark.
The above output transistor has a large driving ability as being used for a signal amplification. A plurality of the output transistors are concurrently driven. If the plural output transistors are also connected to the single ground line
7
, then an internal circuit is influenced in power voltage or power potential. In order to avoid this influence to power voltage or power potential, it is generally adopted that a power is supplied to the output transistors separately from the internal circuit, for which reason separately from the ground pad
101
and the power voltage pad
104
for supplying the ground potential and the power voltage to the internal circuit, there are additionally provided an additional ground potential pad
102
and an additional power potential pad
105
for supplying the ground potential and the power voltage to the output transistors. The n-channel output transistors
5
are connected through a ground potential supply line
8
to the additional ground potential pad
102
. The p-channel output transistors
6
are connected through a power voltage supply line
33
to the additional power potential pad
105
.
FIG. 2
is a fragmentary plane view illustrative of a layout of a circuit block
4
′ which is connected to the input/output pad
103
in
FIG. 1
, wherein the circuit block
4
′ includes the input/output pad
103
, the diode
2
, the voltage clamping device
3
, and the n-channel output transistor
105
.
FIG. 3
is a fragmentary cross sectional elevation view illustrative of a circuit block
4
′ taken along a B-B′ line of FIG.
3
.
As described above, the semiconductor device has a three-layered well structure over a p-type semiconductor substrate
25
. An n-type well
10
is formed in the p-type semiconductor substrate
25
. Further, p-type wells
91
and
92
are formed in the n-type well
10
so that the p-type wells
91
and
92
are separated from each other. In the p-type well
91
, n-type diffusion layers
11
are selectively formed. The n-type diffusion layers
11
are defined by field oxide films
26
. In the n-type diffusion layers
11
, there are formed the diode
2
for the electrostatic discharge protection circuit and the voltage clamping device
3
. In the p-type well
91
, a guard ring
161
is further provided as a well contact for biasing the well. This guard ring
161
comprises a p+-type diffusion layer. This guard ring
161
is connected through a contact
23
, a tungsten line
15
, and a contact
35
to the ground line
7
. The diode
2
is formed between the p-type diffusion layer unitary formed with the guard ring
161
and the n-type diffusion layer
11
. The guard ring
161
serves as an anode whilst the n-type diffusion layer
11
serves as a cathode. The voltage claming device
3
may be considered to be a bipolar transistor. Adjacent two of the n-type diffusion layers
11
separated from each other by the field oxide film
26
serve as an emitter and a collector of the bipolar transistor and the p-type well
91
serves as a base.
In the p-well
92
, an n-channel output transistor
5
is formed which comprises an n-type diffusion layer
12
and a gate electrode
13
. A source of the output transistor
5
is connected through a contact
24
, a tungsten line
34
and a contact
22
to the ground potential supply line
8
. A drain of the output transistor
5
is connected through a contact
21
, a tungsten line
14
and a contact
19
to the input/output pad
103
. In this well
92
, a guard ring
162
is formed which comprises a p+-type diffusion layer. This guard ring
162
is connected to the ground potential supply line
8
.
An n-well contact
17
is formed to bias the n-well
10
. This n-well contact
17
is also connected to a DVV line. A p-type substrate contact
18
is also formed in the p-type substrate
25
. Those substrate contact and the well contacts are provided in order to prevent that carriers generated in an electrostatic voltage application are transmitted through the substrate to break a gate oxide film and a pan junction existing in the peripheral region.
FIG. 4
is a plane view illustrative of a conventional semiconductor pellet. A pellet
32
has a memory block
29
and a peripheral circuit
31
. The memory block
29
includes memory cell arrays, address decoders and sense amplifiers. We peripheral circuit
31
includes a voltage-rising circuit or a boosting circuit and a voltage-falling circuit for a power supply, a data amplifier and fuse circuits for re
NEC Corporation
Ngo Ngan V.
Young & Thompson
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