Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-18
2004-10-05
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S362000
Reexamination Certificate
active
06800906
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a protection circuit. More particularly, the present invention relates to an electrostatic discharge protection circuit applied in high voltage device manufacturing processes.
2. Description of Related Art
Semiconductor manufacturers and electronic device users continue to demand faster, increasingly complex devices in smaller packages at lower costs. In order to meet those demands, semiconductor manufacturers keeps shrinking geometries of the devices. As the devices turn compact and clearances and line widths approach theoretical limits, devices are becoming increasingly susceptible to damage by electrostatic discharge (ESD). Short, fast, high-amplitude ESD pulses are an inevitable part of the day-to-day environment of both chips and equipment. In fact, ESD is the leading cause of device failure in the field. The destructive mechanism associated with ESD in devices is primarily melting of the device material due to high temperatures. Due to the nature of ESD, it must be assumed that all devices will encounter an event during the normal course of their lifetime. Hence, ensuring that devices provide a reasonable and acceptable level of tolerance to ESD is an important part of all device design and manufacturing programs.
To determine the ESD threshold of a device, it is necessary to agree on the type of ESD stress for which testing will take place. There are presently three major ESD stress types: Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). For HBM, the threshold voltage can be as high as 2 KV, while the threshold voltage for MM is around 200V.
FIG. 1A
is a circuit diagram of the conventional diode protection circuit. From
FIG. 1A
, three terminals, including Vcc terminal
1
, input/output (I/O) terminal
2
and Vss terminal
3
can be used to measure (or test) the voltage. Normally, the conventional diode protection circuit consists of two n-diodes and one p-diode.
FIG. 1B
is a schematic cross sectional view of the conventional diode protection circuit containing two n-diodes and one p-diode, applied in the high voltage (HV) manufacture processes. A provided P-type substrate (P substrate)
100
contains three separate wells, including a high voltage (HV) N-well
102
formed between two HV P-wells
104
,
106
. In the HV N-well
102
, a P− region
110
is separate from and between two N+ regions
114
,
116
near both sides of the HV N-well
102
. A P+ region
112
is formed in the HV N-well
102
and encompassed by the P− region
110
. Switching into different dopant types forms similar sub-regions in HV P-wells. The HV P-well
104
includes an N− region
120
, a N+ region
122
encircled within the N− region, two separate P+ regions
124
,
126
near both sides of the HV P-well
104
. The N− region
120
is separate from and between two separate P+ regions
124
,
126
. Also, the HV P-well
106
includes an N− region
130
, a N+ region
132
encircled within the N− region, two separate P+ regions
134
,
136
near both sides of the HV P-well
106
. The N− region
130
is separate from and between two separate P+ regions
134
,
136
. The N+ regions
114
,
122
are coupled to the Vcc terminal
1
, while the P+ regions
126
,
134
are coupled to the Vs terminal
3
. The P+ region
112
and the N+ region
132
are coupled to the I/O terminal
2
.
In this case, the conventional diode protection circuit, containing two n-diodes and one p-diode applied in the high voltage (HV) manufacture processes, has a rather high breakdown voltage, thus providing very little protection for high voltage devices. Furthermore, the conventional diode protection circuit depends on the p-diode between the Vcc terminal
1
and I/O terminal
2
for bypassing large ESD current, which can easily damage junction damage or cause contact spiking.
SUMMARY OF THE INVENTION
The invention provides an ESD protection circuit compatible with the high voltage device manufacturing processes by using parasitic bipolar junction transistor (BJT) punch characteristics. The design of the present invention takes advantage of bipolar punch characteristics of the parasitic NPN or PNP bipolar structure to bypass the ESD current, thus significantly increasing the ESD level. In addition, the ESD protection circuit of the present invention can greatly reduce the ESD cell areas by eliminating certain prior art diode structure.
As embodied and broadly described herein, the invention provides an electrostatic discharge (ESD) protection circuit, comprising: an N substrate having four separate wells, including a high voltage (HV) N-well between a first HV P-well and a second HV P-well and a third HV P-well, the first HV P-well comprising a first P+ region and the second HV P-well comprising a second P+ region, the HV N-well further comprising: a first N− region and a first N+ region disposed within and encompassed by the first N− region, and the third HV P-well further comprising: a third and a fourth P+ regions near both sides of the HV P-well; a second N− region separate from and between the third and fourth P+ regions; and a second N+ region disposed within and encompassed by the second N− region.
As embodied and broadly described herein, the invention provides an ESD protection circuit, comprising: a P substrate having four separate wells, including a first HV N-well arranged between a first HV P-well and a second HV P-well and a second HV N-well, the first HV P-well comprising a first P+ region and the second HV P-well comprising a second P+ region, the first HV N-well further comprising: a first N− region and a first N+ region disposed within and encompassed by the first N− region, and the second HV N-well further comprising: a second and a third N+ regions near both sides of the HV N-well; a first P− region separate from and between the second and third N+ regions; and a third P+ region disposed within and encompassed by the first P− region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4757363 (1988-07-01), Bohm et al.
patent: 4937639 (1990-06-01), Yao et al.
patent: 5181091 (1993-01-01), Harrington et al.
patent: 5481129 (1996-01-01), DeJong et al.
patent: 5652455 (1997-07-01), Zambrano
patent: 5708289 (1998-01-01), Blanchard
patent: 5777367 (1998-07-01), Zambrano
J.C. Patents
Nadav Ori
United Microelectronics Corp.
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