Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-09
2004-07-27
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000
Reexamination Certificate
active
06768176
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor integrated circuit technology. More particularly, the present invention relates to an integrated circuit for electrostatic discharge protection.
Random or transient over-voltage, most commonly in the form of electrostatic discharge (ESD), can harm or even permanently damage an integrated circuit. An ESD event is often associated with a sudden release of a large amount of energy that can easily damage sensitive integrated circuit (IC) components. Protection circuits that can handle such sudden surges of energy are therefore often integrated with sensitive IC components to dissipate the energy. Although electrostatic discharge protection circuits are most often used to protect input and output circuitry, other types of applications may also be necessary and possible.
The most commonly used ESD protection circuits are themselves integrated circuits and built as a part of a larger integrated circuit that has the components intended to be protected. The use of such electrostatic discharge protection circuits is known in the art, as taught, for example, in U.S. Pat. Nos. 5,850,095 and 6,268,649, and other references cited therein.
Although a complete ESD protection circuit may include multiple clamp stages, an essential part of the circuit often includes a Zener diode and a transistor as shown in
FIG. 1
, which is a schematic illustration of such a circuit. As shown in
FIG. 1
, the protection circuit
10
includes a Zener diode
12
, a bipolar transistor
14
, a resistor
16
and a pair of connection terminals
18
and
18
′. Under a normal condition where the voltage between the connection terminals
18
and
18
′ is a relatively small positive voltage, Zener diode
12
is reverse-biased and is “off.” As the voltage reaches a breakdown level, Zener diode
12
experiences a Zener breakdown and is turned on, As a current flows through Zener diode
12
and subsequently resistor
16
, a voltage drop is created across resistor
16
and also across the base and the emitter of transistor
14
, thus forward biasing the base-emitter junction and turning on transistor
14
. When turned on, transistor
14
bypasses a large amount of current that would have been undertaken by the other part of the integrated circuit (not shown in the
FIG. 1
) and avoids potential damages to the integrated circuit that is meant to be protected.
Various designs have been proposed in the art to implement the above protection circuit. Examples of such designs are found in U.S. Pat. Nos. 5,850,095 and 6,268,649, and other references cited therein. Although prior art designs differ from each other, they can be characterized by a simplified scheme represented in FIG.
2
.
FIG. 2
illustrates a cross-section of a typical prior art implementation of a protection circuit based on a Zener diode and a transistor. Protection circuit
20
is built on substrate
21
and has a N− type body layer
22
, an implanted P− base region
24
, N+ diffusion regions
26
,
28
, and
30
, and P+ diffusion region
32
. In this structure, N+ diffusion region
26
, a part of P− base region
24
and N+ diffusion region
28
form a transistor that is represented by transistor
14
in
FIG. 1. A
path (not shown) in P− base region
24
leading to P+ diffusion region
32
forms a resistor that is represented by resistor
16
in
FIG. 1
, whereas N+ diffusion region
30
and a part of P− base region
24
form a Zener diode that is represented by Zener diode
12
in FIG.
1
.
Specifically, according to the scheme illustrated in
FIG. 2
, trigger Zener diode
12
is effected by placing an N+ diffusion region
30
in a P+ base diffusion region
24
. One of the problems of this configuration is that during the N+ implanting, plasma damages in localized areas often occur, causing trap states which result in inconsistency and variability in the silicon band gap in regions that form the PN junction of the Zener diode. Due to trap assisted tunneling, this inconsistency and variability in the silicon band gap can result in a large variability in leakage current as a function of voltage in a reverse biased Zener diode. The large variability in leakage current undermines the process of fabricating integrated circuits. Because the process of fabricating includes making multiple integrated circuits on the same wafer, and additionally a single integrated circuit may itself contain multiple protection circuits, the variability makes the behavior of the integrated circuit products unpredictable and less uniform. Furthermore, leakage currents in a reversed-biased Zener diode are a mixture of the avalanche and tunneling processes. Local area plasma damage that creates significant tunneling effect can therefore result in unacceptably low values, in addition to the large variability thereof, for reverse breakdown voltages of the Zener diodes.
BRIEF SUMMARY OF THE INVENTION
The present invention is an over-voltage protection circuit. The over-voltage protection circuit includes a semiconductor body layer having a first type conductivity, a semiconductor transistor contacting the body layer, and a semiconductor diode formed in the body layer. The transistor has a base region of a second type conductivity opposite to the first type conductivity, a collector region of the first type conductivity and an emitter region of the first type conductivity. The diode has a junction of a first semiconductor region having the first type conductivity and a second semiconductor region having the second type conductivity. The first region of the diode junction is conductively connected to the collector region of the transistor. The second region of the diode junction is conductively connected to the emitter region of the transistor. According to the present invention, the first region of the diode is disposed outside of the base region of the transistor.
In one embodiment, both the first and the second regions of the diode are disposed outside of the base region of the transistor. In another embodiment, both the first and the second regions of the diode are disposed below the base region of the transistor. In yet another embodiment, the first and the second regions of the diode are buried layers disposed outside of the base region of the transistor and forming a side-by-side junction.
REFERENCES:
patent: 5432368 (1995-07-01), Jimenez
patent: 5789785 (1998-08-01), Ravanelli et al.
patent: 5850095 (1998-12-01), Chen et al.
patent: 6268639 (2001-07-01), Li et al.
patent: 785576 (1997-07-01), None
Fourson George
Kebede Brook
Kinney & Lange , P.A.
PolarFab LLC
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