Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-22
2001-06-05
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S173000
Reexamination Certificate
active
06242780
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is in the field of electrostatic discharge (ESD) protection circuit, and is more specifically directed to an ESD circuit with a field oxide device (FOD).
2. Description of the Prior Art
Electrostatic protection is an important field of integrated circuits. The ESD protection circuit is used to protect chips from damage caused by a large current and a large voltage, especially from external charges.
There are many varieties of ESD protection circuit, and one useful variety of ESD circuits is the FOD kind ESD protection circuit that uses a field oxide device and a PN diode. As usual, parasitic bipolar is also used to conduct current from the pad into the substrate.
The equivalent circuit diagram of the FOD kind ESD protection circuit is shown in FIG.
1
. As
FIG. 1
shows, a current (charger) is conducted through input terminal
10
, internal input buffer
11
and internal chips
12
. Moreover, FOD
13
and first diode
14
are located between input terminal
10
and internal input buffer
11
, and is in sequence with internal input buffer
11
. Besides, first diode
14
connects to VDD
15
and FOD
13
is connected to VSS
16
, and second diode
17
is located between VDD
15
and VSS
16
. Herein, the normal state of both FOD
13
and first diode
14
are off, and when the external current appears they are turned on to conduct the current such that the external current will not be conducted into chips
12
.
The structure of the conventional FOD kind of ESD protection circuit is shown in
FIG. 2
, where a qualitative cross section view is provided. As
FIG. 2
shows, there are several isolations
21
located in and on the surface part of substrate
20
, where isolations
21
are used to isolate each structure that locates in and on the surface part of the substrate
20
. Moreover, FOD
13
comprises first region
22
, field oxide
23
, second region
24
and third region
25
; first diode
14
comprises fourth region
26
and fifth region
27
; and second diode
17
comprises sixth region
28
and seventh region
29
. Besides, input terminal
10
connects to first region
22
and fifth region
26
; VDD
15
connects to both fifth region
27
and seventh region
29
; VSS
16
connects to second region
24
, third region
25
and sixth region
28
. Additionally, second diode is located on first well
293
and FOD
13
is located on second well
296
. Herein conductive type of first well
293
is equal to second well
296
but is opposite to conductive type of substrate
20
. Further, conductive type of third region
25
, fourth region
26
and sixth region
28
are equal to conductive type of first well
293
, but conductive type of first region
22
, second region
24
, fifth region
27
and seventh region
29
are equal to substrate
20
.
Comparing FIG.
1
and
FIG. 2
, it is clear that when external charge is applied, avalanche breakdown appears in drain of FOD
13
(first region
22
) and then a parasitic bipolar is formed inside the substrate
10
. Herein parasitic bipolar is used to let charge be conducted into substrate
10
(substrate
10
acts as a ground). Owing to the fact that the turn on rate of the parasitic bipolar is not fast enough, first diode
14
and second diode
15
will be forward biased to share an external charger until the parasitic bipolar is turned on.
Because the depth of each region is finite, the junction cross-section area also is finite and then current density cannot be arbitrarily decreased. Therefore, owing to the fact that power is proportional to current and current density is higher in the surface part the of substrate
10
, it is especially higher in neighboring corners of two regions of the same diode. Local heating is an unavoidable result and will induce contact melting such that material of contact (such as metal) is melted, and then melted material flows into a neighboring well and induces short of ESD protection circuit. Obviously, the local heating is more serious when shallow junction is required and the current path is concentrated in the surface of substrate
10
.
According to the previous discussion, an unsolved issue of the conventional ESD protection circuit is the local heating phenomena. Because ESD protection circuit will be degraded or even be invalidated, it is desired to overcome the unsolved issue such that the circuit's lifetime is prolonged and performance is improved.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a structure of FOD kind ESD protection circuit.
It is another object of the invention to provide such an ESD protection circuit that efficiently reduces the effect of local heating phenomena.
It is a further object of the invention to provide an ESD protection circuit that is applicable with shallow junction.
It is still a further object of the invention to provide a manufacturable structure of ESD protection circuit.
In order to explain the invention, an embodiment is used to present a specific structure of ESD protection circuit that efficiently prevents the issue of local heating.
The content of the embodiment is described as follows: First, the equivalent circuit of the invention is equal to the conventional FOD kind of ESD protection circuit, and the basic structure also is similar to a conventional ESD protection circuit. Second, in order to overcome the local heating phenomena, deep junction is applied to form a drain-like region of each diode and a drain-like region of FOD. Thus, junction cross-section area is increased and current density is decreased. Besides, owing to the fact that energy of the carrier is higher in the depletion area of the drain-like region, the heating effect is efficiently reduced. Moreover, the deep junction also permits distribution of an electric field is far away from the surface of the substrate. Third, low doped density junction is used to form drain-like regions of all diodes and a drain-like region of FOD. Owing to the fact that current density of the junction is proportional to doped density of the junction, current density is further decreased. Of course, owing to the restriction of integration of the fabrication process, drain-like regions of all diodes and the drain-like region of FOD can be formed as a low doped density junction with a high doped junction that is located on the low doped density junction.
In conclusion, the main characteristic of the invention is that deep junction is used to increase junction cross-section area of all diodes and the FOD. Therefore, not only is the resistivity of each diode decreased but also distribution of the electrical field of each diode is also far away from the surface of the substrate. Thus, diode local heating is efficiently decreased and the lifetime of the proposed ESD circuit is prolonged.
REFERENCES:
patent: 5637900 (1997-06-01), Ker et al.
Mintel William
Nadav Ori
United Microelectronics Corp.
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