Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-09-06
1998-11-10
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257355, 257356, 257357, 257362, H01L 2362
Patent
active
058359869
ABSTRACT:
Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section. By matching the width of the ESD device to the sum of the length of the driver section and the width of the surrounding guard ring, latchup of the SCR structure in the ESD protection device may be inhibited or eliminated, since any charges injected into the substrate from outer source regions in the MOS structure of the driver section and passing through the guard ring region will not impact against the width dimension of the ESD protection device. At the same time, such matching of the width of the ESD protection device to the total length of the MOS structure of the driver section and the width of the guard ring permits the overall size or footprint of the driver section to be reduced by reduction of the physical width of the MOS structure of the driver section without reduction of the effective width of the MOS structure of the driver section, so that the driver section is still capable of handling the required input or output power.
REFERENCES:
patent: 3748187 (1973-07-01), Aubuchon et al.
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5535084 (1996-07-01), Nakayama
Kapoor Ashok K.
Wei Hua-Fang
Loke Steven H.
LSI Logic Corporation
Taylor John P.
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