Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2006-11-28
2008-12-23
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S087000, C361S056000
Reexamination Certificate
active
07468617
ABSTRACT:
In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.
REFERENCES:
patent: 2005/0230751 (2005-10-01), Ohta et al.
Huang Cheng-Hsiung
Sengupta Samit
Wu Wei-Guang
Altera Corporation
Barnie Rexford
Morgan & Lewis & Bockius, LLP
Tran Thienvu V
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